MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 9817
BEGIN_KEYWORDS
SPECIAL_ISSUE PHYSICAL_DESIGN
END_KEYWORDS
DATE: July 1998
TITLE: PHYSICAL DESIGN SPECIAL ISSUE

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      VLSI DESIGN:  An International Journal of
                    Custom-Chip Design, Simulation, and Testing

                     JOURNAL

            published by Gordon and Beach Science Publishers
 
                           Call For Papers
 
           Special Issue on Physical Design in Deep Submicron
 
  Objective
  ----------
 
     As physical feature sizes decreases, the time delay of electrical signals
  traveling in the interconnect between active devices and gates is approaching
  the delay through the devices and gates.  The parasitic information of the
  interconnect is absolutely critical to predicting circuit performance.
     Thus, physical interconnections delay will overtake gate delays as a design
  concern by the tear 2000, mandating a shift in the physical design flow for
  deep-submicron.  Therefore, Iterations between synthesis and layout increase
  dramatically due to timing and routability problems.
     The key to solving this problem is knowing more about the physical design,
  i.e., placement and estimated interconnect, early in the design cycle.
  The RTL is being defined to accurately predict size, timing and power,
  early in the design cycle and avoid downstream iterations.  This means the
  design engineer needs to get back to the fundamentals of physics.
    It is the goal of this special issue to explore physical level solutions to
  the deep submicron problems.
 
  Areas of Interests
  ------------------
 
  Innovative technical papers are solicited, but not limited to.
 
           1.  Layout problems in System on Silicon
           2.  Timing-driven hierarchical place-and-route
           3   Advanced routing for deep submicron technologies
           4.  Parasitic extraction and delay calculation
           5.  Lower power physical optimization
           6.  Clock/Power issues in deep submicron
           7.  Logic/RTL synthesis predicting physical constraints
           8.  Physical design database management
           9.  Reliability Issues due to huge design density
 
  We also invite one or two papers to be tutorial
  reviews.
 
  Instructions to Authors
  -----------------------
 
      Authors are invited to submit a compressed and uuencoded
      postscript file by E-mail (or three hard copies by surface mail) of
      an original, unpublished paper by Monday, September 7, 1998 to:
 
             Jun-Dong Cho, Guest Editor
             School of Elec. and Comp. Eng.
             Sungkyunkwan University
             300 Chunchun-Dong Jangan-Ku
             Suwon, Korea 440-746
             (tel): 0331-290-7127
             (fax): 0331-290-7170
             jdcho@yurim.skku.ac.kr
 
  Notification of acceptance will be mailed by Nov. 20, 1998.
  Accepted papers will be printed as the Journal for the year 2000 volume.
 
       We encourage submissions from work in progress.
 
 
  Editor In Chief
  ---------------
 
  Dr. George W. Zobrist
  Department of Missouri-Rolla
  Rolla, Missouri 65401
  FAX: (314) 341-4501
  E-mail: zobrist@umr.edu
 
  Regional Editors
  ----------------
 
  Dr. Bayoumi, USA Editor (digital signal processing)
           University of Southwestern Louisiana, Lafayette, Louisiana
  Dr. Hideaki Kobayashi, USA Editor (VLSI design methodologies)
          University of South Carolina, Columbia, South Carolina
  Dr. C. P. RaviKumar, Indian Editor (VLSI physical design)
          Indian Institute of Technology, New Delhi, India
  Dr. Raul Camposano, European Editor (High level synthesis)
          GMD/EIS and University of Paderhorn, Sankt Augustin, Germany
  Dr. Sunil R. Das, Canadian Editor (VLSI testing)
          University of Ottawa, Ottawa, Canada
  Dr. Lalit Patnaik, Southeast Asia Editor (Layout algorithms)
          Indian Institute of Science, Bangalore, India
  Dr. Hiroto Yasuura, Japanese Editor (High level synthesis)
          Kyushu University, Kasuga, Fukuoka, Japan
 
  Editorial Advisory Board
  ------------------------
  Dr. Ramon Acosta,
          International Software Systems, Inc., Austin, Texas
  Dr. Don Bouldin,
          Unversity of Tennessee, Knoxville
  Dr. Melvin A. Breuer,
          University of Southern California, Los Angeles
  Dr. Ralph K. Cavin, III,
         North Carolina State University, Raleigh
  Dr. Narsingh Deo,
          University of Central Florida, Orlando
  Dr. Srinivas Devadas,
          MIT, Cambridge, MA
  Dr. Fausto Distante,
          Politechnico di Milano, Italy
  Dr. Hideo Fujiwara,
          Advanced Institute of Science and Technology, Japan
  Dr. Huey-Liang Hwang,
          National Tsing-Hua University, Hsin-Tsu, Taiwan
  Dr. Marwan jabi,
          University of Sydney, Australia
  Dr. Osamu Karatsu,
          NTT-LSI Laboratories, Atsugi-shi, Japan
  Dr. Amar Mukherjee,
          University of Central Florida, Orlando
  Dr. Sabuo Muroga,
          University of Illinois, Urbana
  Dr. Stephan Olariu,
          Old Dominion University, Norfolk, Virginia
  Dr. C. V. Ramamoorthy,
          University of California, Berkeley
  Dr. Andrew Sage,
          George Mason University, Fairfax, Virginia
  Dr. L. Spaanenburg,
          University of Groningen, Netherlands
  Dr. Victoria Stavridou,
          University of London, Suurey, UK
  Dr. Leon Stok,
          IBM T. J. Watson Research Center, Yorktown Heights, NY
  Dr. Earl Swartzlander,
          University of Texas, Austin
  Dr. Philip A. Wilsey,
          University of Cincinnati, Ohio
  Dr. Mehmet Yanilmaz (Book Review Editor),
          Comtek Consultants Group, Inc.,Evanston, Illinois
  Dr. Si-Qing Zheng,
          Louisiana State University, Baton Rouge
 
  For further information concerning the special issue, please contact:
  Jun Dong Cho, Guest-Editor.
 


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