MICROELECTRONIC SYSTEMS NEWS
FILENUMBER: 9821
BEGIN_KEYWORDS
MOSIS
END_KEYWORDS
DATE: July 1998
TITLE: MOSIS: BSIM3v3 AND 0.5-MICRON SOI
=======================================================================
From XMOSIS@mosis-chip.isi.edu Tue Jun 16 03:54 EDT 1998
Subject: MOSIS support for SPICE BSIM3v3
MOSIS now provides SPICE BSIM3v3 parameters for all MOSIS
sub-micrometer CMOS technologies. Parameters extracted and optimized
for each CMOS fabrication run processed through MOSIS are available at
MOSIS.
BSIM3v3, which has been adopted widely throughout the semiconductor
industry, explicitly incorporates short and narrow channel, graded
junction, and poly depletion effects, with performance in the
subthreshold and transition regions superior to that of earlier
models. Many BSIM3v3 parameters are linked to physical device
characteristics, and with only a few binning parameters it is possible
to simulate with reasonable accuracy a wide range of device sizes.
MOSIS will no longer produce BSIM1 (HSPICE Level 4) parameters.
For some period of time MOSIS will continue to publish lot-specific
SPICE Level 3 parameters for technologies with feature sizes 1.0
micrometer and larger.
We are considering discontinuing support for SPICE Level 3 in May 1999
or earlier. MOSIS users who would be adversely affected by the absence
of MOSIS-generated Level 3 parameters should contact us by sending
electronic mail to support@mosis.org or calling 1.310.822.1511,
extension 403.
For a summary of the limitations of SPICE Level 3, please see the file
submicron-spice-parameters.inf (via FTP from MOSIS at
ftp/pub/mosis/info).
Regards,
MOSIS Customer Support
Phone: (310) 822-1511 x403, Fax: (310) 823-5624
USC/ISI, 4676 Admiralty Way, Marina del Rey, CA 90292
MOSIS
===
From XMOSIS@mosis-chip.isi.edu Tue Jun 30 04:22 EDT 1998
Subject: 0.5 micron SOI Prototypes
MOSIS is pleased to announce a qualification run with the Peregrine
Semiconductor SOI (SOS) 0.5um 3-metal process for September.
Peregrine Semiconductor (www.peregrine-semi.com) offers a production
SOI (specifically SOS) technology that provides solutions for RF,
Analog mixed signal and low voltage digital applications. Peregrine's
patented UTSi CMOS process is manufactured in a volume Japanese fab
with yields consistent with other CMOS products being built in the fab.
The 0.5um process supports digital densities of up to 400k gates at
0.4uW/MHz/gate. This same process has RF performance of >50 GHz Fmax
operating at 3 volts and below. Because of the Sapphire substrate,
excellent resistors, capacitors and inductors (Q of 10 at 1 GHz) are
available for mixed signal and RF applications. The Sapphire substrate
isolation offers unparalleled levels of integration unachievable with
traditional silicon solutions.
Examples of production products are the PE3292- 1 volt, 1 GHz, 3.9 mW
dual fractional-N Phase Locked Loop and the PE3320- 2 GHz highly
linear downconverter based upon +24 IIP3 mixer technology.
UTSi CMOS also provides superior solutions for rad hard applications
with 100k total dose capability as well as 1E-9 SEU tolerance. SEU
performance is especially important for PLL's in todays satellites
that can use anywhere from 500 to 1,000 PLL's per satellite. UTSi CMOS
is latch up immune.
We would like your feedback on this process. At a minimum, please
provide estimates of the number of projects and their sizes.
Thank you for your time and consideration. Please respond by sending a
message to support@mosis.org. We would like to receive all responses
by July 6. If you are unable to provide a response by that date please
send it at your earliest convenience.
=======================================================================
dbouldin@utk.edu
Return to MSN Home Page