MICROELECTRONIC SYSTEMS NEWS
FILENUMBER: 9825
BEGIN_KEYWORDS
DESIGN_REUSE
END_KEYWORDS
DATE: July 1998
TITLE: DEVELOPMENTS IN DESIGN REUSE
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TITLE: DEVELOPMENTS IN DESIGN REUSE
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(Contributed by Don Bouldin of the Univ. of Tennessee)
Modern silcon manufacturing processes have enabled the cost-
effective production of multi-million transistor chips. However,
computer-aided design tools have not kept pace so the transistors
on these chips often are not all customized but instead have been
ported from previous designs. These reusable cores include MPEG
decompression engines, PCI bus controllers, specialized DSPs,
etc. Combining several complex cores using gates and standard
cells is much more manageable and quicker than designing millions
of transistors one at a time.
Over the past two years, there has been a general recognition in
the design community of the need and value of reusable cores or
intellectual property (IP) blocks. It was certainly one of the
hottest topics at this year's Design Automation Conference.
Several panel sessions were held and many exhibitors were showing
off their latest wares. The remarks below reflect my own opinion
of what is going on between the lines. Anyone wishing to comment
should email me at d.bouldin@ieee.org.
The software industry has been tackling this problem for some
time. Dr. Barry Boehm of the Univ. of Southern California has
statistics (see NIST) on software
reuse that indicates that it takes about 50% more effort to
prepare code for reuse than if it is a one-time event. However,
the next designer benefits by a 70% reduction in his time. Thus,
reuse still requires a significant amount of time to integrate
and verify in the new environment. The big payoff is in the
reduced time-to-market which is known to lead to higher revenues.
Cell-based ASIC companies like LSI Logic, Motorola, and IBM
already have a lot of IP blocks which they regularly reuse from
one internal project to another. This internal reuse is
faciliated by the absence of any legal barriers, access to the
original designers and CAD tools, multi-levels of representation
including the physical layout, and the ability to fabricate the
layout in-house. These vendors recognize that a block must be
fully documented and be "known good" just as multiple dies in a
multi-chip module.
ASIC customers outside of these companies are interested in
getting access to these valuable blocks but are generally told
they must use the fabrication capability of the company owning
the IP. This provides a low-risk path for the customer but may
come without competititve pricing.
To avoid this potentially captive situation, an open market is
being set up by more than 100 electronics firms who have joined
together to form the Virtual Socket Interface (VSI) Alliance.
(See VSI). This group seeks to develop the
technical standards required to enable the interfacing of
intellectual property blocks from multiple sources. The intent
is to create worldwide IP networks that will facilitate the use
of system-level macros, cores or megacells. The establishment of
the VLSI Alliance has been endorsed by an association of IP
providers, RAPID (see RAPID).
System-chip designers can already access a web-based network at
DESIGN-REUSE to identify IP sources; evaluate
alternatives for performance, cost, quality, and risk; and then
quickly complete the appropriate internal or external transaction
to receive all required information for design-in of the chosen
IP. Candidate sources of IP include internal corporate design
groups, located at any site around the world, semiconductor
vendors, EDA vendors, and independent IP providers.
IP in standardized "virtual component" forms will be rapidly
mixed and matched into system chips. Common interface standards
will allow virtual components to fit quickly into "virtual
sockets," at both the functional level (e.g., interface
protocols) and the physical level (e.g., clock, test, and power
structures). In addition, IP design data standards will be based
on de facto, open formats supported by all EDA vendors. As such
IP providers will need only to productize and maintain one set of
IP deliverables, rather than the many sets of deliverables
required today to support unique customer design flows.
In addition to the standards efforts being conducted by the VSI
Alliance, IEEE has formed a group with essentially the same
purpose but with a longer-term view (see
IEEE-STD).
Third-party IP providers like Sand Microelectronics (See
SAND) and Phoenix Technologies Virtual Chips
(See PHOENIX) are suppliers of IP blocks.
However, this potentially lower cost path comes with higher risk
in that integration of the core may not succeed without expensive
support. So, a designer may have to accompany the IP block in
order to be certain that it gets integrated properly.
FPGA vendors like Xilinx, Altera and Actel appear to be offering
customers limited IP blocks for free as an enticement to
purchasing their silicon devices.
Design houses often list their IP blocks to show their experience
and hence that they are likely to implement similar projects
quickly and successfully. However, they rarely reuse the IP
block without altering it to some degree.
CAD tool companies like Mentor Graphics and Synopsys are taking
steps to help their customers design for reuse and be able to
integrate IP blocks easily. They have joined together to publish
a book of guidelines entitled "Reuse Methodology Manual for
System-On-A-Chip Designs" (see WKAP for ISBN: 0-
7923-8175-0).
Cadence Design Systems, however, is taking a different approach
with its expansion into design services. The customer retains
rights to the final design which may be fabricated by a variety
of ASIC foundries but Cadence retains lower-level IP blocks for
reuse in other projects. This approach enhances productivity for
Cadence designers.
Security of IP blocks is an issue that has been raised. Several
watermark proposals were presented at DAC and recorded in the
Proceedings (See DAC).
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dbouldin@utk.edu