MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 9841
BEGIN_KEYWORDS
TEXT VERILOG SYNTHESIS BHASKER
END_KEYWORDS
DATE: December 1998
TITLE:  NEW TEXT ON VERILOG SYNTHESIS BY BHASKER


=================================================================
TITLE:  NEW TEXT ON VERILOG SYNTHESIS BY BHASKER

"Verilog HDL Synthesis: A Practical Primer" by J. Bhasker is  now
available  from  Star  Galaxy  Publishing.   The  book,  ISBN  0-
9650391-5-3, retails for US$49.95.  While its predecessor book "A
Verilog  HDL Primer" focuses on the Verilog language, this book's
focus is on synthesis.

With this book, you can expect to learn:

a. How registers and nets map to wires,  flip-flops  or  latches?
b.  How  each construct in Verilog maps to what hardware?  c. How
to avoid simulation mismatches?  d. How to write  Verilog  models
for  best  performance?  e. An example of a synthesizable Verilog
HDL subset.  f. Examples of synthesizable hardware blocks.

Here are some reader's comments:

"Provides students and practicing logic designers with  immediate
access to well organized information about Verilog HDL synthesis.
Easy  to  read  and  provides  a  large  number  of  examples  of
synthesizable Verilog models"
  - Vassilios Gerousis, Senior Staff Technologist, Motorola

"Ideally   organized   for   teaching   Verilog-based   synthesis
techniques, as it shows the reader not only what hardware results
from various Verilog constructs,  but  also  how  to  tailor  the
Verilog to get the desired hardware"
  - Jim Vellenga, Viewlogic Systems

"Reveals  a  variety  of  situations  where  differences  between
simulation and synthesis are bound to occur ... carefully covered
so that novice and experienced designers become  aware  of  these
hard to debug but very common pitfalls."
  - Carlos Roman, Bell Labs

"Excellent,  clear  and   concise   guide   for   designing   RTL
synthesizable models"
  - Douglas J. Smith, Author of "HDL Chip Design"

"The example-driven approach used makes it a  valuable  book  for
novice Verilog users."
  - Egbert Molenkamp, University of Twente, the Netherlands


For ordering info and table of contents, access:

 WWW


=================================================================


 

Return to MSN Home Page  
 dbouldin@utk.edu