MICROELECTRONIC SYSTEMS NEWS
FILENUMBER: 9844
BEGIN_KEYWORDS
TEXT VERILOG SYNTHESIS CILETTI
END_KEYWORDS
DATE: December 1998
TITLE: NEW TEXT ON VERILOG SYNTHESIS BY CILETTI
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TITLE: NEW TEXT ON VERILOG SYNTHESIS BY CILETTI
Access: WWW
"Modeling, Synthesis, and Rapid Prototyping with the VERILOG HDL"
by Michael D. Ciletti, University of Colorado at Colorado Springs
Coming December, 1998 from Prentice Hall Engineering, Science & Math
Copyright 1999, 500 pp. Cloth
ISBN 0-13-977398-3
Designed for undergraduate computer science, computer
engineering and electrical engineering courses in digital
design and hardware description languages, this textbook
presents an integrated treatment of the Verilog hardware
description language (HDL) and its use in VLSI, circuit
modeling/design, synthesis, and rapid prototyping.
Shows the use of Verilog HDL in digital design and
synthesis using examples (e.g., FIFO-based data acquisition
system design, microcontroller design, electronic game
design, and client-server polling circuit design). Source
code files for examples are included. Examples are
encapsulated complete and the source code has been tested.
Illustrates descriptive styles that synthesize and
identifies pitfalls that either prevent synthesis or lead
to unexpected and undesirable results.
Includes results of simulation and synthesis.
Over 250 complete and carefully chosen examples.
Special Feature: "Xilinx Student Software (Foundations Series Express 1.5"
and the SILOS Verilog circuit simulator (demonstration version) are packaged with the book
providing a complete learning environment.
SUPPLEMENT = Includes discount coupon to purchase optional FPGA hardware.
Problems and design exercises at the end of chapters. o Includes ASIC cell library.
[Table Of Contents]
1. Introduction to Electronic Design Automation.
Electronic Design Automation. A Brief History of HDLs.
The Role and Requirements of HDLs in EDA. Benefits of
Using HDLs in EDA. Summary.
2. Hardware Modeling with the Verilog HDL.
Hardware Encapsulation: the Verilog Module. Hardware
Modeling: Verilog Primitives. Descriptive Styles.
Structural Connections. Behavioral Descriptions in
Verilog. Hierarchical Descriptions of Hardware.
Structured (Top-Down) Design Methodology. Using
Verilog for Synthesis. Language Conventions.
Representation of Numbers. Summary.
3. Testbenches and Event-Driven Simulation.
Simulation with Verilog. Design Unit Testbench.
Summary.
4. Logic System, Data Types, and Operators for Modeling in
Verilog HDL.
Variables. Logic Value Set. Data Types. Strings.
Constants. Operators. Expressions. Operator
Precedence. Summary.
5. User-Defined Primitives.
UDP: Combinational Behavior. UDP: Sequential Behavior.
Summary.
6. Verilog Models of Propagation Delay.
Built-In Constructs for Delay. Signal Transitions.
Verilog Models for Gate Propagation Delay (Inertial
Delay). Time Scales for Simulation. Verilog Models for
Net Delay (Transport Delay). Module Paths and Delays.
Paths Delays and Simulation. Inertial Delay Effects
and Pulse Rejection. Summary.
7. Behavioral Descriptions in Verilog HDL.
Behaviors. Procedural Statements. Procedural
Assignment. Procedural Continuous Assignment.
Non-blocking Assignment. Procedural Timing Controls.
Intra-Assignment Delay. Event-Scheduling Scheme.
Repeated Intra-Assignment Delay. Indeterminate
Assignments and Ambiguity. Simulator Processing Steps.
Flow Control. Tasks and Functions. Summary of Delay
Constructs in Verilog. The wait Statement. Parallel
Activity Flow: The fork...join Statement. Race
Conditions and the fork...join Statement. Summary of
Delay Constructs in Verilog. Variable Scope Revisited.
Module Contents. Finite State Machines. Summary.
8. Synthesis of Combinational Logic.
HDL-Based Synthesis. Technology-Independent Design.
Benefits of Synthesis. Synthesis Methodology. Vendor
Support. Styles for Synthesis of Combinational Logic.
Technology Mapping and Shared Resources.
9. Synthesis of Sequential Logic.
Synthesis of Sequential UDPs. Synthesis of Latches.
Synthesis of Edge-Triggered Flip-Flops. Registered
Combinational Logic. Shift Registers and Counters.
Synthesis of Finite State Machines. Asynchronous
Resets. Synthesis of Gated Clocks. Busses. Synthesis
of Buffered Outputs. Design Partitions and
Hierarchical Structures.
10. Synthesis of Language Constructs.
Synthesis of Nets. Synthesis of Register Variables.
Restrictions on Synthesis of "x" and "z". Synthesis of
Expressions. Synthesis of Arithmetic Operators.
Synthesis of Non-Arithmetic Operators. Synthesis of
Assignments. Synthesis of case and Conditional
Statements. Delay Controls in Synthesis. Synthesis of
Event Control Expressions For Combinational Logic.
Synthesis of Event Control Expressions for Sequential
Logic. Multiple Event Controls. Synthesis of the wait
Statement. Synthesis of Named Events. Synthesis of
Multi-cycle Operations. Synthesis of Loops. Synthesis
of fork...join Blocks. Synthesis of the disable
Statement. Synthesis of User-Defined Tasks. Synthesis
of User-Defined Functions. Synthesis of Specify
Blocks. Synthesis of Compiler Directives.
11. Switch-Level Models in Verilog.
MOS Transistor Technology. Switch-Level Models of MOS
Transistors. Switch-Level Models of Static CMOs
Circuits. Alternative Loads and Pull Gates. CMOs
Transmission Gates. Bi-Directional Gates (Switches).
Signal Strengths. Ambiguous Signals. Strength
Reduction by Primitives. Combination and Resolution of
Signal Strengths. Signal Strengths and Wired Logic.
12. Design Examples in Verilog.
13. Rapid Prototyping with Xilinx FPGAs.
Appendixes.
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