MICROELECTRONIC SYSTEMS NEWS
FILENUMBER: 9853
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TEXT VHDL SYNTHESIS ROMDHANE MADISETTI HINES
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DATE: December 1998
TITLE: TEXT ON VHDL CORE SYNTHESIS BY ROMDHANE, MADISETTI AND HINES
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TITLE: TEXT ON VHDL CORE SYNTHESIS BY ROMDHANE, MADISETTI AND HINES
"Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis"
by Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
ISBN 0-7923-9744-4
First published in June, 1996, the text describes how VLSI chips can be designed
within a VHDL-based synthesis environment using a pre-designed core component library.
This library of synthesizable units of behavior (function and control) are both
application-specific and organization-specific. The co-authors (Rockwell, Georgia Tech,
and the US Air Force Wright Laboratories) insert the key to open the door to
quick-turnaround through systematic reuse; accurate power, speed, area, and timing
information percolation that facilitates design space facilitation; and the integration
and testing of ASICs into board level designs. The illustrations detail cost models
and design implementation.
KLUWER
Kluwer Academic Publishers
P.O. Box 17, 3300 AA Dordrecht, the Netherlands
Phone: (+31) 78 639 23 92
Fax: (+31) 78 639 22 54
E-mail: Services@wkap.nl
or
101 Philip Drive, Norwell, MA 02061, U.S.A.
Phone: +1 781 871 6600
Fax: +1 781 871 6528
E-mail: kluwer@wkap.com
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dbouldin@utk.edu
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