=================================================================
TITLE: 0.18-MICRON CMOS AVAILABLE VIA CMP
CMP introduces the HCMOS8 .18u CMOS process from STMicroelectronics
(Crolles, France).
CMP
The HCMOS8 process has the following features:
Gate length : .18u (drawn), .15u (effective)
Triple well
Power supply 1.8 V
Threshold voltages : VTN = 420 mV, VTP = 400 mV
Isat : TN @ 1.8 V : 600 uA/um TP @ 1.8 V : 280 uA/um
6 metal layers + local interconnect
Low k inter-level dielectric
Low leakage / low power and 3.3 V power supply options are also available.
Design kits are supported under Cadence, Synopsys, Eldo and Hspice.
Full custom designs are supported using Virtuoso layout editor and LAS synthesizer.
The layout verifications (DRC, ERC, extraction, LVS) are fully supported for Diva
and Calibre. Transistor-level simulations are supported under Eldo level 59, and
Hspice level 50.
Standard-cell designs are supported using Verilog/VHDL descriptions for synthesis
and simulation. Synthesis is supported under Synopsys. Simulation is supported
under Verilog-XL, Leapfrog and VSS. The automatic place & route is supported
under Silicon Ensemble suite of tools.
This process is available for prototyping to Education Institutions and Research
Laboratories, on a cooperation basis. No commercial designs are accepted at this
early stage. It is expected that later on, the process will be available on a
commercial basis for small volume production to Education Institutions,
Research Laboratories and specified Companies. A .15u process would then be made
available for Education and Research.
[]
=================================================================
FILENUMBER: 9878
BEGIN_KEYWORDS
0.18-MICRON CMOS CMP
END_KEYWORDS
DATE: December 1999
TITLE: 0.18-MICRON CMOS AVAILABLE VIA CMP
Return to MSN Home Page