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TITLE: PROFESSOR'S KIT FROM WESTERN DESIGN CENTER
The Western Design Center, Inc. (WDC) has created a Professor's
Kit that is intended for the professor to create derivative
teaching material and information that is optimized for their
teaching environment. WDC will provide copyrighted materials and
a W65C122S Learning Kit for the professor's use in developing
course curriculum using WDC's 65C02 IP.
The W65C122S is a system-chip design that includes encrypted
Verilog behavioral models of WDC's W65C02 8-bit MPU, W65C22 I/O,
and 256K RAM and 4K ROM modules. The professor can then create
derivative teaching materials to distribute, under license, to
the student for SOC design. A standard cell library has been
created for the memory map logic, On-Chip Bus (OCB) interface and
off-chip I/O ring. WDC's standard cells are IO, inverters, NOR
gates, and NAND gates. For manufacturing system chips and
protection of WDC's IP, WDC has licensed both MOSIS and Tanner
Research for dropping in and verifying system chips that reuse
WDC IP cores. This is a step in the procurement of system chips
from wafer foundries accessed through MOSIS' multiproject and
small volume fabrication service. After wafer fabrication,
system chips will be provided to the professor, student or
researcher who designed the system-chip (SOC). The analysis of
the W65C122S system-chip is performed in WDC's W65C134 Developer
Board (W65C134DB) as a plug-replacement for WDC's W65C134
microcontroller. The test program is supported by the on-chip
monitor, and debug circuitry. When interfacing with industry
standard ATE, test vectors are created from the in-circuit test
programs when simulated using the Verilog test bench.
For additional information, access:
WWW
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