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TITLE: EDA SOFTWARE FOR UNIVERSITIES
Several electronic design automation companies listed below
have university programs
which provide software for educational purposes at substantial discounts
over retail prices. An annual maintenance fee payment and a report on
how the software was used in courses are generally required.
ALDEC
Active-HDL is a complete design and verification environment that includes
HDL, Block Diagram and State Machine Editors, Automatic Testbench Generation,
Behavioral VHDL & Verilog Simulation (line by line source code debugging),
TCL/TK scripting with direct interface to logic synthesis and FPGA/CPLD
vendor place and route tools, a graphical Waveform Viewer and Editor
and structural simulation supporting Vital 95, SDF and EDIF netlist timing
simulation. Universities can receive a network license and an interactive
VHDL tutorial. Student editions are also available. Access:
ALDEC
CADENCE
The Cadence Design Systems university program provides software in
functional bundles: custom integrated circuits, deep submicron, design &
verification and printed circuit board systems. One or more of the bundles
can be obtained for an annual maintenance fee of $5000. Access:
CADENCE
Web pointers to universities using Cadence software are provided at:
Universities using Cadence
MENTOR GRAPHICS
Over 400 colleges and universities worldwide are using Mentor Graphics
software. Tutorials and design kits for fabrication via MOSIS are provided.
MENTOR GRAPHICS
Web pointers to universities using Mentor Graphics software are provided at:
U.S. Universities using Mentor Graphics
SYNOPSYS
The predominant synthesis package provided by Synopsys is available
to qualified universities throughout the world. Access:
SYNOPSYS
XILINX
Over 1000 educational institutions are supported by this program which
includes not only software but courseware and prototyping hardware.
Access:
XILINX
ALTERA
Software, prototyping hardware and textbooks are part of this
extensive program. Access:
ALTERA
SYNPLICITY
This program provides synthesis software for FPGA/CPLD design. Access:
SYNPLICITY
FRONTIER DESIGN
Digital signal processing algorithms can be described using fixed-point
arithmetic in a special version of the C language. An automatic
conversion to synthesizable VHDL or Verilog is then made.
Access:
FRONTIER DESIGN
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FILENUMBER: 9937
BEGIN_KEYWORDS
EDA SOFTWARE UNIVERSITIES
END_KEYWORDS
DATE: August 2000
TITLE: EDA SOFTWARE FOR UNIVERSITIES
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