----------------------------------------------------------------------------
--File: 	design_tb.vhd
--Date: 	September 13, 2001
--Version: 	3.0
--
--Purpose:	This is a simple testbench for design_top.vhd
--	It first reads from all locations from both ports.
--	Then, it writes to all locations from one port while reading from the other.
----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testbench is
end testbench;

architecture simulate of testbench is

component design_top
		PORT (
			AddressA : in  std_logic_vector (7 DOWNTO 0);
			AddressB : in  std_logic_vector (7 DOWNTO 0);
			CLKA : in  std_logic;
			CLKB : in  std_logic;
			Data_inA : in  std_logic_vector (63 DOWNTO 0);
			Data_inB : in  std_logic_vector (63 DOWNTO 0);
			Data_outA : out  std_logic_vector (63 DOWNTO 0);
			Data_outB : out  std_logic_vector (63 DOWNTO 0);
			EnableA : in  std_logic;
			EnableB : in  std_logic;
			Write_EnableA : in  std_logic;
			Write_EnableB : in  std_logic
		);
	END COMPONENT;

-- Initialize all inputs
	SIGNAL AddressA : std_logic_vector (7 DOWNTO 0);
	SIGNAL AddressB : std_logic_vector (7 DOWNTO 0);
	SIGNAL CLKA : std_logic;
	SIGNAL CLKB : std_logic;
	SIGNAL Data_inA : std_logic_vector (63 DOWNTO 0);
	SIGNAL Data_inB : std_logic_vector (63 DOWNTO 0);
	SIGNAL Data_outA : std_logic_vector (63 DOWNTO 0);
	SIGNAL Data_outB : std_logic_vector (63 DOWNTO 0);
	SIGNAL EnableA : std_logic;
	SIGNAL EnableB : std_logic;
	SIGNAL Write_EnableA : std_logic;
	SIGNAL Write_EnableB : std_logic;
        SIGNAL ADDRPAD       : std_logic_vector (3 downto 0);
        SIGNAL DATAPAD       : std_logic_vector (47 downto 0);

begin

--Instantiation of module being simulated
UUT : design_top
PORT MAP (
	AddressA => AddressA,
	AddressB => AddressB,
	CLKA => CLKA,
	CLKB => CLKB,
	Data_inA => Data_inA,
	Data_inB => Data_inB,
	Data_outA => Data_outA,
	Data_outB => Data_outB,
	EnableA => EnableA,
	EnableB => EnableB,
	Write_EnableA => Write_EnableA,
	Write_EnableB => Write_EnableB
);


-- pad the first 4 bits of addra and addrb to 0

ADDRPAD <= (others => '0');
DATAPAD <= (others => '0');

AddressA(7 downto 4) <= ADDRPAD;
AddressB(7 downto 4) <= ADDRPAD;
Data_inA(63 downto 16) <= DATAPAD;
Data_inB(63 downto 16) <= DATAPAD;


--------------------------------------------
--Generation of both clocks
--------------------------------------------
clocka : PROCESS
begin
	CLKA <= '1';
   	wait for 20 ns;
	CLKA <= '0';
	wait for 20 ns;
end process;

clockb : PROCESS
begin
	CLKB <= '1';
   	wait for 15 ns;
	CLKB <= '0';
	wait for 15 ns;
end process;

--------------------------------------------
--Stimulus
--------------------------------------------
initialize : PROCESS
begin

--Start Block Ram Read
--Shows what the Block Ram 1st sixteen address data values
--were initialized to by the COE file.
-- Reads are done through port A then port B

	ENABLEA <= '1';
	ENABLEB <= '1';
	WRITE_ENABLEA <= '0';
	WRITE_ENABLEB <= '1';
	Data_inA(15 downto 0) <= "0000000000000000";
	Data_inB(15 downto 0) <= "0000000000000000";

	--read from initialized RAM for A and B side in opposite order
	ADDRESSA(3 downto 0) <= "0000";
	ADDRESSB(3 downto 0) <= "1111";
      wait for 41 ns;
	ADDRESSA(3 downto 0) <= "0001";
      ADDRESSB(3 downto 0) <= "1110";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "0010";
      ADDRESSB(3 downto 0) <= "1101";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "0011";
      ADDRESSB(3 downto 0) <= "1100";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "0100";
      ADDRESSB(3 downto 0) <= "1011";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "0101";
	ADDRESSB(3 downto 0) <= "1010";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "0110";
	ADDRESSB(3 downto 0) <= "1001";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "0111";
	ADDRESSB(3 downto 0) <= "1000";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "1000";
	ADDRESSB(3 downto 0) <= "0111";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "1001";
	ADDRESSB(3 downto 0) <= "0110";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "1010";
	ADDRESSB(3 downto 0) <= "0101";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "1011";
	ADDRESSB(3 downto 0) <= "0100";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "1100";
	ADDRESSB(3 downto 0) <= "0011";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "1101";
	ADDRESSB(3 downto 0) <= "0010";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "1110";
	ADDRESSB(3 downto 0) <= "0001";
	wait for 40 ns;
	ADDRESSA(3 downto 0) <= "1111";
	ADDRESSB(3 downto 0) <= "0000";
	wait for 40 ns;

--Start Block Ram Write the Read
-- write value of X to address X on B port while reading from port A after write is complete
	wait for 60 ns;
	Write_EnableB <= '1';

	ADDRESSB(3 downto 0) <= "0000";
	Data_inB(15 downto 0) <= "0000000000000000";
	wait for 30 ns;
	
	ADDRESSB(3 downto 0) <= "0001";
	Data_inB(15 downto 0) <= "0000000000000001";
	wait for 30 ns;	

	ADDRESSA(3 downto 0) <= "0000";
	wait for 10 ns;

	ADDRESSB(3 downto 0) <= "0010";
	Data_inB(15 downto 0) <= "0000000000000010";
	wait for 30 ns;

	ADDRESSA(3 downto 0) <= "0001";
	wait for 10 ns;
	
	ADDRESSB(3 downto 0) <= "0011";
	Data_inB(15 downto 0) <= "0000000000000011";
	wait for 30 ns;
	
	ADDRESSA(3 downto 0) <= "0010";
	wait for 10 ns;


	ADDRESSB(3 downto 0) <= "0100";
	Data_inB(15 downto 0) <= "0000000000000100";
	wait for 30 ns;

	
	ADDRESSA(3 downto 0) <= "0011";
	wait for 10 ns;

	ADDRESSB(3 downto 0) <= "0101";
	Data_inB(15 downto 0) <= "0000000000000101";
	wait for 30 ns;

	ADDRESSA(3 downto 0) <= "0100";
	wait for 10 ns;
	

	ADDRESSB(3 downto 0) <= "0110";
	Data_inB(15 downto 0) <= "0000000000000110";
	wait for 30 ns;
	

	ADDRESSA(3 downto 0) <= "0101";
	wait for 10 ns;
	
	ADDRESSB(3 downto 0) <= "0111";
	Data_inB(15 downto 0) <= "0000000000000111";
	wait for 30 ns;

	
	ADDRESSA(3 downto 0) <= "0110";
	wait for 10 ns;

	ADDRESSB(3 downto 0) <= "1000";
	Data_inB(15 downto 0) <= "0000000000001000";
	wait for 30 ns;
	
	ADDRESSA(3 downto 0) <= "0111";
	wait for 10 ns;

	
	ADDRESSB(3 downto 0) <= "1001";
	Data_inB(15 downto 0) <= "0000000000001001";
	wait for 30 ns;

	
	ADDRESSA(3 downto 0) <= "1000";
	wait for 10 ns;

	ADDRESSB(3 downto 0) <= "1010";
	Data_inB(15 downto 0) <= "0000000000001010";
	wait for 30 ns;

	
	ADDRESSA(3 downto 0) <= "1001";
	wait for 10 ns;

	ADDRESSB(3 downto 0) <= "1011";
	Data_inB(15 downto 0) <= "0000000000001011";
	wait for 30 ns;
	
	ADDRESSA(3 downto 0) <= "1010";
	wait for 10 ns;

	
	ADDRESSB(3 downto 0) <= "1100";
	Data_inB(15 downto 0) <= "0000000000001100";
	wait for 30 ns;
	
	ADDRESSA(3 downto 0) <= "1011";
	wait for 10 ns;

	
	ADDRESSB(3 downto 0) <= "1101";
	Data_inB(15 downto 0) <= "0000000000001101";
	wait for 30 ns;

	
	ADDRESSA(3 downto 0) <= "1100";
	wait for 10 ns;

	ADDRESSB(3 downto 0) <= "1110";
	Data_inB(15 downto 0) <= "0000000000001110";
	wait for 30 ns;
	
	ADDRESSA(3 downto 0) <= "1101";
	wait for 10 ns;

	
	ADDRESSB(3 downto 0) <= "1111";
	Data_inB(15 downto 0) <= "0000000000001111";
	wait for 30 ns;
 
	ADDRESSA(3 downto 0) <= "1110";
	wait for 40 ns;

	Write_EnableB <= '0';

	ADDRESSA(3 downto 0) <= "1111";
	wait for 10 ns;


end process;

end simulate;