----------------------------------------------------------------------------
--File: 	design_top.vhd
--Date: 	September 13, 2001
--Version: 	3.0
--
--Purpose:	This is an instantiation of the core dpbr, which is a core from the 
--Xilinx Core Generator software.  The core is the Dual Port Block RAM V3.1 core.
----------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity design_top is
    Port ( AddressA : in std_logic_vector(7 downto 0);
           AddressB : in std_logic_vector(7 downto 0);
	   CLKA     : in std_logic;
	   CLKB     : in std_logic;
           Data_inA : in std_logic_vector(63 downto 0);
	   Data_inB : in std_logic_vector(63 downto 0);
           Data_outA : out std_logic_vector(63 downto 0);
	   Data_outB : out std_logic_vector(63 downto 0);
	   EnableA : in std_logic;
	   EnableB : in std_logic;
	   Write_EnableA : in std_logic;
	   Write_EnableB : in std_logic);
end design_top;

architecture behavioral of design_top is

component ram64_256
	port (
	addra: IN std_logic_VECTOR(7 downto 0);
	addrb: IN std_logic_VECTOR(7 downto 0);
	clka: IN std_logic;
	clkb: IN std_logic;
	dina: IN std_logic_VECTOR(63 downto 0);
	dinb: IN std_logic_VECTOR(63 downto 0);
	douta: OUT std_logic_VECTOR(63 downto 0);
	doutb: OUT std_logic_VECTOR(63 downto 0);
	ena: IN std_logic;
	enb: IN std_logic;
	wea: IN std_logic;
	web: IN std_logic);
end component;



begin


My_DUAL_PORT_RAM : ram64_256
		port map (
			addra => AddressA,
			addrb => AddressB,
			clka => CLKA,
			clkb => CLKB,
			dina => Data_inA,
			dinb => Data_inB,
			douta => Data_outA,
			doutb => Data_outB,
			ena => EnableA,
			enb => EnableB,
			wea => Write_EnableA,
			web => Write_EnableB);

end behavioral;