================================================================= (BOLD HEADING) Advanced IC Processes Being Developed By Intel Intel presently manufactures its Pentium-4 processor in high- volume production using a 90-nm CMOS process. However, new high-k mails are being developed to provide dielectrics thinner than silicon dioxide. Using just five atomic layers, high-k insulation can be made a mere 1.2-nm thick. Making the dielectric ever thinner is necessary in order to meet increasing performance goals. When the gate dielectric of a transistor thins, its insular quality decreases and current leaks through it. Uncontrolled, this conduction causes the transistor to stray from its purely "on" and "off" state and into an "on" and "leaky off" behavior. Intel announced recently that it has already built fully functional SRAM chips using a 65-nm CMOS process and is on track for high-volume production in 2005 using 300 mm wafers. This new process combines higher-performance and lower-power transistors with eight layers of copper interconnects and low-k dielectrics so that Intel can double the number of transistors it can build on a single chip today. Thus, Intel expects to extend its 15-year record of ramping production on a new process generation every two years. The 65-nm process uses transistors with gate lengths of only 35-nm whereas 50-nm gate lengths are used in today's Pentium-4 processors. The process supports memory cells with a density of 10-million transistors per square millimeter. Intel's 300-mm development fab is located in Hillsboro, Oregon, and has a 176,000 sq. ft. cleanroom, which is roughly the size of 3.5 football fields. For additional information, access: http://www.intel.com/research/silicon (BOLD HEADING) Resolution Enhancement for Optical Lithography Optical lithography distortions that occur in the manufacture of integrated circuits are being addressed by multiple techniques. Since the early 1970's, optical proximity correction or OPC has been used to produce smaller features in an IC using a given equipment set. OPC applies systematic changes to photomask geometries to compensate for nonlinear distortions caused by optical diffraction and resist process effects. Specifically, these distortions include line-width variations dependent on pattern density which affect a device's speed of operation and line-end shortening which can break connections to contacts. Causes include reticle pattern fidelity, optical proximity effects, and diffusion and loading effects during resist and etch processing. A mask incorporating OPC is thus a system that negates undesirable distortion effects during pattern transfer. OPC works by making small changes to the IC layout that anticipate the distortions. To compensate for line-end shortening, the line is extended using a hammerhead shape that results in a line in the resist that is much closer to the original intended layout. To compensate for corner rounding, serif shapes are added to (or subtracted from) corners to produce corners in the silicon that are closer to the ideal layout. Determining the optimal type, size, and symmetry (or lack thereof) is very complex and depends on neighboring geometries and process parameters. A sophisticated computer program is necessary to properly implement OPC. Proper OPC provides for an enhanced process window for both dense and isolated lines. It provides wider process latitude for an existing process or creates a process window for a new, smaller feature process. OPC enables significant savings through extending the lifetime of existing lithography equipment. OPC offers basic corrections and a useful amount of yield improvement. For additional information, access: http://www.synopsys.com/products/ntimrg/opc_ds.html (BOLD HEADING) Chemical Mechanical Polishing Designers should be aware of the layout requirements imposed by Chemical Mechanical Polishing or CMP. The move to deep sub-micron processes has placed conflicting requirements on the photolithographic systems employed by wafer vendors. The feature size of the process is directly proportional to the numerical aperture of the lenses used for printing while the depth-of- field of the lenses is inversely proportional. Hence, this situation has forced wafer manufacturers to implement severe planarity requirements on their deep sub-micron processes which can only be achieved by using CMP. CMP removes material from uneven topography on a wafer surface until a flat (planarized) surface is created, allowing subsequent photolithography to take place with greater accuracy and enabling film layers to be built up with minimal height variations. CMP combines the chemical removal effect of an acidic or basic fluid solution with the "mechanical" effect provided by polishing with an abrasive material. The CMP system usually has a polishing "head" that presses the rotating wafer against a flexible pad. A wet chemical slurry containing a micro-abrasive is placed between the wafer and pad. It is the designer's responsibility to achieve a minimum density on various layers to provide the necessary structural support for this process. If the design does not intrinsically contain sufficient density, then additional "fill" material should be used. However, the designer must be careful not to use this material in such a way that the primary circuit is affected. CMP is performed primarily in the interconnect structure of the chip, where it is used multiple times. CMP is especially critical for the fabrication of copper wiring structures. This advanced planarization capability enables chipmakers to continue shrinking circuits and extends the performance of lithographic tools. For additional information, access: http://www.appliedmaterials.com/products/about_cmp_process.html (BOLD HEADING) Process-Induced Damage or Antenna Rules During manufacture, the gate oxide may become damaged when exposed polysilicon and metal structures collect charge from the processing environment (e.g., reactive ion etch) and develop potentials sufficiently large to cause Fowler-Nordheim current to flow through the thin oxide. This process-induced damage is generally referred to as "antenna rules". Given the known process charge fluence, a figure of exposed conductor area to transistor gate area ratio is determined which guarantees time-dependent dielectric breakdown reliability requirements for the fabricator. Failure to consider antenna rules in a design may lead to either reduced transistor performance or to total failure if the antenna rules are seriously violated. There are layout techniques to help deal with antenna ratio rules. For example, if a design uses a large array of clocked devices connected to a single clock source via a metal1 clock distribution structure then a "cut and link" method can be used to moderate the antenna rule effects. In this method, the metal1 distribution structure is divided up into pieces of metal1 connected to gate structures such that the antenna rule is obeyed. Short links from metal1 to metal2 then back to metal1 connect the clock distribution structure in a way that it prevents the total area of the clock distribution structure from being connected to gate poly structures during metal1 etch. Specific numbers for the antenna ratio rules are contained in design rules for each fabricator. MOSIS customers can obtain this information by accessing: http://www.mosis.org/Technical/Designrules/guidelines.html []