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Design Synthesis using Synopsys Design Compiler
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(b) Synthesis with test, Scan Insertion using Synopsys DC (Design Compiler)
    Invoke Synopsys Design Compiler in the shell mode (scan insertion can only be done in the shell mode)
    dc_shell -db_mode -dcsh_mode -f leon_dc_new_scan
    This will start DC in the shell mode and all the commands after this have to be entered in the
    dc_shell> prompt.

(b) Set the correct target and search libraries for synthesis
    search_path = "/usr/cad/course/ibm_pc_astro/2006/LM /usr/cad/course/ibm_pc_astro/2006/leon_rams"
    target_library = /usr/cad/course/ibm_pc_astro/2006/LM/slow.db
    link_library = "/usr/cad/course/ibm_pc_astro/2006/LM/slow.db /usr/cad/course/ibm_pc_astro/2006/leon_rams/dpram136x32_inst_slow.db ram256x32_inst_slow.db ram32x30_inst_slow.db"

(c) Set the following constraints for the netlist format,
    link_force_case = "check_reference"; gen_match_ripper_wire_widths = "true";
    bus_dimension_separator_style = {][}; bus_range_separator_style = ":"
    Define the power and ground port names
    edifout_power_port_name = "VDD"; edifout_ground_port_name = "VSS"

(d) Enable HDL presto for compiling VHDL files, create a work directory for storing certain synthesis files
    and define the design library
    hdlin_enable_presto_for_vhdl = true; hdlin_ff_always_sync_set_reset = true; hdlin_translate_off_skip_text = true
    sh rm -rf WORK; sh mkdir WORK; define_design_lib WORK -path WORK

(e) Analyze all the VHDL and Verilog files for syntax errors and RTL translation. Scan insertion is done top down for the Leon SoC.
    analyze -format VERILOG -library WORK ../leon/timescale.v
    analyze -format VHDL -library WORK ../leon/rijndael_pkg.vhdl
    analyze -format VHDL -library WORK ../leon/key_sched_iterative.vhdl
    analyze -format VHDL -library WORK ../leon/alg_iterative.vhdl
    analyze -format VHDL -library WORK ../leon/controller_iter.vhdl
    analyze -format VHDL -library WORK ../leon/interface.vhdl
    analyze -format VHDL -library WORK ../leon/RIJNDAEL_Top_Iterative.vhdl
    analyze -format VHDL -library WORK ../leon/aes_top.vhd
    analyze -format VERILOG -library WORK ../leon/dpram136x32_box0.v
    analyze -format VERILOG -library WORK ../leon/dpram136x32_box1.v
    analyze -format VERILOG -library WORK ../leon/ram32x30_box0.v
    analyze -format VERILOG -library WORK ../leon/ram256x32_box0.v
    analyze -format VHDL -library WORK ../leon/amba.vhd
    analyze -format VHDL -library WORK ../leon/target.vhd
    analyze -format VHDL -library WORK ../leon/device.vhd
    analyze -format VHDL -library WORK ../leon/config.vhd
    analyze -format VHDL -library WORK ../leon/sparcv8.vhd
    analyze -format VHDL -library WORK ../leon/mmuconfig.vhd
    analyze -format VHDL -library WORK ../leon/iface.vhd; analyze -format VHDL -library WORK ../leon/macro.vhd
    analyze -format VHDL -library WORK ../leon/bprom.vhd; analyze -format VHDL -library WORK ../leon/aes_ctrl.vhd
    analyze -format VHDL -library WORK ../leon/aes.vhd; analyze -format VHDL -library WORK ../leon/multlib.vhd
    analyze -format VHDL -library WORK ../leon/tech_generic.vhd
    analyze -format VHDL -library WORK ../leon/tech_virtex.vhd
    analyze -format VHDL -library WORK ../leon/tech_virtex2.vhd
    analyze -format VHDL -library WORK ../leon/tech_atc18.vhd
    analyze -format VHDL -library WORK ../leon/tech_atc25.vhd
    analyze -format VHDL -library WORK ../leon/tech_atc35.vhd
    analyze -format VHDL -library WORK ../leon/tech_fs90.vhd
    analyze -format VHDL -library WORK ../leon/tech_tsmc25.vhd
    analyze -format VHDL -library WORK ../leon/tech_ibm.vhd
    analyze -format VHDL -library WORK ../leon/tech_umc18.vhd
    analyze -format VHDL -library WORK ../leon/tech_proasic.vhd
    analyze -format VHDL -library WORK ../leon/tech_axcel.vhd
    analyze -format VHDL -library WORK ../leon/tech_map.vhd
    analyze -format VHDL -library WORK ../leon/cachemem.vhd
    analyze -format VHDL -library WORK ../leon/icache.vhd
    analyze -format VHDL -library WORK ../leon/dcache.vhd
    analyze -format VHDL -library WORK ../leon/acache.vhd; analyze -format VHDL -library WORK ../leon/cache.vhd
    analyze -format VHDL -library WORK ../leon/ambacomp.vhd
    analyze -format VHDL -library WORK ../leon/apbmst.vhd
    analyze -format VHDL -library WORK ../leon/ahbmst.vhd; analyze -format VHDL -library WORK ../leon/ahbstat.vhd
    analyze -format VHDL -library WORK ../leon/ahbtest.vhd; analyze -format VHDL -library WORK ../leon/ahbram.vhd
    analyze -format VHDL -library WORK ../leon/ahbarb.vhd; analyze -format VHDL -library WORK ../leon/lconf.vhd
    analyze -format VHDL -library WORK ../leon/fpulib.vhd; analyze -format VHDL -library WORK ../leon/fpu_lth.vhd
    analyze -format VHDL -library WORK ../leon/meiko.vhd; analyze -format VHDL -library WORK ../leon/fpu_core.vhd
    analyze -format VHDL -library WORK ../leon/ioport.vhd; analyze -format VHDL -library WORK ../leon/irqctrl.vhd
    analyze -format VHDL -library WORK ../leon/sdmctrl.vhd; analyze -format VHDL -library WORK ../leon/mctrl.vhd
    analyze -format VHDL -library WORK ../leon/rstgen.vhd; analyze -format VHDL -library WORK ../leon/timers.vhd
    analyze -format VHDL -library WORK ../leon/uart.vhd; analyze -format VHDL -library WORK ../leon/mul.vhd
    analyze -format VHDL -library WORK ../leon/div.vhd; analyze -format VHDL -library WORK ../leon/iu.vhd
    analyze -format VHDL -library WORK ../leon/dcom_uart.vhd
    analyze -format VHDL -library WORK ../leon/dcom.vhd
    analyze -format VHDL -library WORK ../leon/dsu_mem.vhd; analyze -format VHDL -library WORK ../leon/dsu.vhd
    analyze -format VHDL -library WORK ../leon/proc.vhd; analyze -format VHDL -library WORK ../leon/wprot.vhd
    analyze -format VHDL -library WORK ../leon/mcore.vhd; analyze -format VHDL -library WORK ../leon/leon.vhd

(f) Elaborate the design, to convert it from the VHDL description into a synopsys specific format required
    for synthesis. Link the design to locate all the library components referenced and connect it to the current design
    elaborate leon; link

(g) Set the current design to leon and uniquify the whole design. In a hierarchical design, sub designs are
    often referenced by more than one cell instance, that is, multiple references of the design can occur.
    The "uniquify" command resolves multiple cell references to the same design in memory. The command creates 
    unique design copies with unique design names for each instantiated cell that referenced the original design
    current_design leon; uniquify

(h) Set the current design to Leon, set up the scan configuration and compile the design to achieve optimization.
    current_design leon; set_scan_configuration -style multiplexed_flip_flop -methodology full_scan -chain_count 10
    current_design leon; compile -scan -map_effort medium

(i) Preview the scan design by typing the following command.
    current_design leon; preview_scan -show all

(j) Report the timing, area and power by typing,
    report_area > area.log; report_timing > timing.tmg; report_power > power.log

(k) Perform a post scan check and check the design against the design rules of a scan test methodology.
    check_test

(l) Save synthesized verilog netlist and STIL files and Quit design compiler.
    write -format verilog -hierarchy -output leon_test.v; write_test_protocol -format stil -output leon_test.spf
    quit