Introduction To Logic Design and Digital Systems


Instructor:  Brad Vander Zanden, x 8175  email:; Claxton 354


Cell Phone Policy:  Cell phones will be turned off during class.


Text:  Fundamentals of Digital Logic Design with VHDL Design, by Brown and Vranesic, 3rd Ed., includes CD ROM for VHDL projects.


Important Dates:

Tue, 10/28



Thu, 12/4




Tentative Topics                                                                                    Reading                       

Introduction to logic design, physical realizations                              ch 1,2   


Boolean algebra, truth tables                                                          ch 2                 

Simplification by Boolean algebra                                                             

Synthesis using NOT, AND, OR gates, design examples      


Introduction to CAD tools, schematic entry, VHDL                           ch 2.10, Appendix A                               


Simplification by Karnaugh maps, don't cares                                   ch 4


Number systems, binary arithmetic                                                             ch 5                 


Adders                                                                                       ch 5.4   


Multiplexers, decoders, encoders                                                    ch 6                   

ROMs, PLAs, PALs, FPGAs                                                                   

More VHDL                  


SR flip-flop, debounce circuits                                                       ch 7                 

master-slave, JK, D flip flop                                                                     

Registers, counters                                                                                  


design of clocked seq circuits:                                                        ch 8                 

design examples with VHDL                                                                    

State equivalence, simplification,                                                               

Mealy/Moore circuits


Timing considerations                                                                  ch  9                

Analysis of asynchronous circuits                                                   ch 9                 

Synthesis of asynchronous circuits             


Design considerations (time permitting)                                           ch. 10


Office Hours:  Tuesday/Thursday 3:30-4:30, or by appointment.


Calculate Your Grade: 

1) Midterm 30%

2) Final 30%

3) Homework 20%

4) Projects 20%: failure to complete all of the projects will result in a failing course grade


Grade Scale

93-100 A, 90-93 A-,

87-90 B+, 83-87 B, 80-83 B-

77-80 C+, 73-77 C, 70-73 C-

60-69 D

<60 F