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"Xilinx Spartan3 examples" templates: /sw/Xilinx8.1i/data/projnav/templates/vhdl.xml /sw/Xilinx8.1i/data/projnav/templates/verilog.xml pong/readme: Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board. DESIGN TYPE: ISE (chip 3s200 FT256-4) CONTROLS (Inputs): clk_ic4 - 50 MHz clock input from on-board oscillator, btn(3) - left most push button on S-3 demo board used as reset for design ps2d - data input from PS2 port ps2c - clock input from PS2 port OUTPUTS: seg_ - 7-segment display for used to display game title, an(3:0) - anode control to determine active seven segment display vga_red - red color signal to VGA monitor vga_blue - blue color signal to VGA monitor vga_green - green color signal to VGA monitor vga_vs - vertical synchronization signal to VGA monitor vga_hs - horizontal synchronization signal to VGA monitor DESCRIPTION: This simple design receives the input from a ps2 keyboard to control the paddles and serve for a pong game. The game is displayed on a VGA monitor. The following keyboard keys are used as controls up arrow key - right paddle up down arrow key - right paddle down w key - left paddle up s key - left paddle down space bar key - serve ball Source Files: pong_top.sch - The top level schematic contains symbolic layout of the pong design including the FPGA pin connections to many of the Spartan3 demo board input, display and port features. pong_cntrl.vhd - This Entity contains the pong game logic testram.vhd - This Entity contains an array of data elements representing VGA display patterns vgacore_multi.vhd - This Entity contains the VGA display control. game_title.v - This module displays the title, PONG, on the four seven segment LEDs of the Spartan3 Demo Board read_ps2.v - This module interprets the scan code from the keyboard and outputs the corresponding signal to move a paddle or serve. ps2_cntrl.v - This module receives the Clock and serial data input from the PS2 port and outputs a Scan Code representing the key entered on the keyboard vga_interface.vhd - This Entity interprets the color output to the VGA monitor Behavioral and RTL Simulation done using Test bench waveform (pong.tbw). NOTE: If you are trying to run this example in a read-only location, the design hierarchy will not display properly. Please copy the example project to a new location by using either Project Save As... from the File menu pulldown in ISE or some other method of your choice. Copy the example to a location where you have write permissions and the hierarchy will display properly. watchvhd_cr2/readme cnt60.vhd hex2led.vhd smallcntr.vhd stmchine.vhd tenths.vhd watch.vhd watch_tb.tbw watch_tb.vhd watch_tb.xwv watchvhd.ise WATCHVHD is a top level VHDL type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip CoolRunner-II) CONTROLS Inputs: * CLK -System clock for the Watch design. * STRTSTOP -Starts and stops the stoopwatch. This is an active-low signal which acts like the start/stop button on a runner's stop-watch. * RESET -Resets the stopwatch to 00.0 after it has been stopped. Outputs: * TENSOUT[6:0] -7-bit bus which represents the Tens digit of the stopwatch value. This bus is in 7-segment display format to be viewable on the 7-segment LED display. * ONESOUT[6:0] -similar to TENSOUT bus above, but represents the Ones digit of the stopwatch value. * TENTHSOUT[9:0] -10-bit bus which represents the Tenths digit of the stopwatch value. This bus is one-hot encoded. DESCRIPTION: * STMACH -State Machine macro. This module uses the VSS StateCAD Editor to enter and implement the state machine. * CNT60 -VHDL-based module which counts from 0 to 59, decimal. This macro has two 4-bit outputs, which represent the 'ones' and 'tens' digits of the decimal values, respectively. * TENTHS -A 10-bit counter. This macro outputs the 'tenths' digit of the watch value. * HEX2LED -HDL-based macro. This macro decodes the ones and tens digit values from hexadecimal to 7-segment display format. SIMULATION: Requires the following simulation libraries: Unisims Simprims Behavioural and RTL Simulation done using Testbench Waveform file(watch_tb.tbw). http://www.xilinx.com/products/boards/DO-SPAR3-DK/reference_designs.htm http://www.xess.com/prod039.php3 * Digitize and display a frame of video with our frame-grabber. * Read and write sectors of a hard disk with our IDE interface. * Sample and playback a stereo audio signal with our audio loopback circuit. * Echo characters received through the serial port with our RS232 interface. * Read and write the SDRAM using our simple SDRAM controller. * Provide multiple read/write channels to the SDRAM using our dualport module. http://wiki.tcl.tk/14116 Xilinx Spartan 3 Demo rs232 clock set I've been working with a Xilinx Spartan-3 demo board[1], for which there is a clock example that can be burned in the config FLASH with little effort, and that clock can be set (and some other things) over an RS-232 link. This tcl script programs the computer clock automatically into the board with a readable command. http://www.cs.colostate.edu/~cs460 http://www.cs.colostate.edu/~cs460/spartan3.html http://www.cs.colostate.edu/~cs460/labnotes/tutorials.html 1. Create parity.vhd. 2. Create top.vhd. http://ece.wpi.edu/~rjduck/ece574.htm ECE 574: Modeling and Synthesis of digital systems using Verilog and VHDL http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-1209946 XAPP774 - Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex™-II or Virtex™-II Pro FPGA. Lower speed ADC devices from this family can be connected to Spartan™-3 FPGAs. Design Files: xapp774.zip Associated Products: Virtex-II Pro,Virtex-II,Spartan-3/3L Version: 1.2 Size: 246Kb Date: 02/23/06 Helpful? Yes | No http://www.synopsys.com/cgi-bin/svp/lib/svpcafe.cgi?vendor=430 The Spartan-3 family is the industry's defacto low cost FPGA platform. The Spartan-3 family is based on advanced 90nm, 8-layer metal process technology. Xilinx is using 90nm technology to drive pricing down to under $12* for a one million gate FPGA and $2.95 for a 50,000 gate FPGA (approximately 17,000 and 1,700 logic cells respectively). Xilinx redefines the logic landscape with the Spartan-3 Platform FPGA family. Built on four generations of proven Spartan success in high volume applications, Spartan-3 FPGAs give you up to 5 million system gates with the lowest cost per gate and per I/O of any FPGA. Visit the Spartan web site to find out more. *Volume pricing for 250k units, end of 2005 http://www.eng.uwaterloo.ca/~tnaqvi/courses/syde192.html http://www.fpga4fun.com/index.html Music box R/C servos Serial interface Text LCD module PWM and one-bit DAC Quadrature decoder Pong game Graphic LCD panel I2C LED displays JTAG Debouncer Advanced projects: Digital oscilloscope 10BASE-T interface PCI interface Spoc CPU core http://6004.csail.mit.edu/currentsemester http://6004.csail.mit.edu/currentsemester/handouts/L24-1up.pdf http://www.eng.auburn.edu/~nelson/courses/elec5250_6250/ http://www.eng.auburn.edu/~nelson/courses/elec5250_6250/FPGA%20Implementations.ppt http://www.cse.unt.edu/~hab/Teaching/CSCE3610/ http://www.cse.unt.edu/~hab/Teaching/CSCE3610/lab2mb.pdf adding ip (microblaze) to spartan3 http://ecen3233.okstate.edu/ http://ecen3233.okstate.edu/Fall%202005/PDF/FPGA%20Tutorial.pdf Lab 1 - Introduction and Full Adder The primary objective of Lab 1 is to introduce you to the laboratory and prototyping. We will discuss digital logic and you will construct and verify the operation of a Full Adder circuit. Be sure to turn in your post-lab documentation at the beginning of your next lab period. Additionally, keep the circuit you have built in this lab. It will be used in Lab 2 Lab 2 - Combinational Logic - N-Bit Full Adder with discrete components and FPGA This lab exercise has two independent parts. The first combines the circuit you and your team members designed and implemented in Lab 1 to form a multi-bit full adder. The second requires you to repeat the design using the FPGA. This lab is to be completed only once by your entire TEAM. The complexity of this project is considerably greater than Lab 1 - don't wait to start! Lab 3 - Combinational Logic - Logic Analyzer This lab exercise requires you to construct three fundamental logic circuits in Xilinx and implement them using an FPGA: the Ring Oscillator, the Full Adder, and the Multiplier, and verify their operation with the logic analyzer. You must take readings such that you can determine the hazards in the logic of the circuits. This lab is to be completed only once by your entire TEAM. Lab 4 - Combinational Logic - FritzLarsonia Motion Indicator Lab 4 presents a word problem and specifications for a portion of an imaginary movement control system. The portion you are to design involves determining the direction of motion on a cylinder based on the current position and the requested position. When a request is made, the circuit will indicate whether the tracking position should move up, down, left, right, or stay on the current position. No provision is made for multiple position requests. You will use switches to input the current position and the requested position. The current position will be displayed on a seven-segment display, and you will also indicate the two directions of motion. This project is to be completed only once by your entire TEAM, as are all laboratory projects for the remainder of the semester. Lab Practical Exam Your Lab Practical Exam will consist of a simple combinational design problem that you will solve and implement during your normal laboratory session time. Each laboratory section will be split into two 50-minute periods with the students divided between the two shortened sessions. This assignment will be completed individually. Lab 5 - Calculator This lab deals with the design of a somewhat more complex circuit consisting of a collection of simpler functions for performing single digit addition and subtraction in the format you would use to enter it into a calculator. This circuit is sufficiently complex that it would be difficult to implement using discrete logic gates as you have done the previous four weeks. You will use the Xilinx Spartan 3 FPGA in lab to implement and test the circuit. This assignment is to be completed only once by your TEAM. Be sure to refer to the supporting documentation for additional information on FPGAs and related topics on the Resources page. Lab 6 - Phase 1 Lab 6 is the final laboratory assignment for the semester. It is a large assignment that will occupy your lab time for the remainder of the course. This is the first of three Phases, to be posted at approximately two week intervals. Check the Resources link for possibly useful information. Lab 6 - Phase 2 Phase 2 of this assignment asks you to continue and enhance the design of your VGA hardware game. Lab 6 - Phase 3 Phase 3 requires that you complete the system and implement a demonstration model of the game. The model should include the monitor and a separate controller. Grading rubrics for the demonstration and documentation will be posted in approximately one week. http://www.xilinx.com/univ/teaching_material.htm http://www.xilinx.com/univ/xup/labsfnd/downldfpga1.htm Xilinx FPGA Design Flow Workshop Materials These materials are available as a single complete two-day download, individually by day, or further split up into individual files to suit your download preferences. You need to download only one of the choices. You may obtain complete lab solutions by contacting XUP. http://www.xilinx.com/products/design_resources/proc_central/grouping/picoblaze.htm PicoBlaze is a fully embedded 8-bit microcontroller macro for the Virtex™ and Spartan™ series of FPGAs and CoolRunner™-II CPLDs. The PicoBlaze reference designs support 57 to 59 different 16- or 18-bit instructions, 8 to 32 general-purpose byte-wide registers, up to 256 directly and indirectly addressable ports, reset, and a maskable interrupt. The PicoBlaze controller for Spartan-3, Virtex-4, Virtex-II, and Virtex-II Pro also include 64 bytes of scratchpad RAM. http://www.xilinx.com/univ/downld_partnerteaching.htm Academic Partner Teaching Material A catalog of high-quality course material is available from a range of partner academic institutions. High quality course lecture notes and laboratory material, along with solutions, are available in source form, PowerPoint or Word. (Note that access to this material requires XUP Member Sign-in) * Logic Design , San Jose State University * DSP-FPGA Primer, Univ. of Strathclyde Syllabus Other representative sampling of high quality teaching material is available from the following sites: * EDK, MPEG 2 System On A Chip; Brigham Young University * Digital Design (EE 108 a), Stanford University * Digital Design (EE 108 b) , Stanford University * Advanced Digital Design, Stanford University * MicroBlaze and Micro CLinux; University of Queensland * Introductory Digital Systems Laboratory using the FPGA Lab Kit: MIT * http://www.eecg.toronto.edu/%7Epc/courses/432/2004/ * http://www.cs.ualberta.ca/~amaral/courses/329/ * Network Processing; Stanford University http://www.stanford.edu/class/ee108a/ http://www-mtl.mit.edu/Courses/6.111/labkit/ The basics: Breadboards, clocks, LEDs, switches, generic i/o signals, and logic analyzer connectors. Audio: An AC'97 codec allows for stereo audio input and output. VGA Video: A dedicated video DAC drives any VGA-compatible monitor. TV Video: Built in video encoder and decoder chips handle composite and s-video input and output. SRAMs: 4MB of high-speed synchronous ZBT memory is soldered onto the labkit PCB. Radio Kit VHDL projects completed--opencores.org http://www.opencores.org/browse.cgi/by_category?filter1=status_stable&filter2=language_vhdl Arithmetic core CORDIC core 5x4Gbps CRC generator designed with standard cells Single Clock Unsigned Division Algorithm FPU Discrete Cosine Transform core Prototype board SD/MMC Bootloader MAXII-Evalboard Communication controller I2C controller core Stepper Motor Controller I2S Interface HDB3/B3ZS Encoder+Decoder Quadrature Decoder / Counter SPDIF Interface Manchester to UART converter SD/MMC Bootloader a VHDL 16550 UART core Coprocessor FPU Crypto core Basic RSA Encryption Engine Basic DES Crypto Core AES128 twofish 128/192/256 AES core modules DSP core FirGen/MultGen ECC core Ultimate CRC Library Random Number Generator Library gh vhdl library Microprocessor Plasma - most MIPS I(TM) opcodes RISC5x T51 mcu System09 Cpu Generator System68 Data Flow Processor JOP: a Java Optimized Processor miniMIPS T400 µController Other First File Reader FAT16 JPEG Hardware Compressor Simple FM Receiver keyboardcontroller xmatchpro lossless data compressor SoC Wishbone System6800/01 System09 WISHBONE Builder ahb system generator

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