------------------------------------------------------------------
-- Author ---> R.Madhan 
--- Test Bench for Cards_Played.vhd
------------------------------------------------------------------
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity Cardplay_tb  is
generic (n: integer := 6); -- number of players
end Cardplay_tb;

architecture tb of Cardplay_tb is

SIGNAL OR_Out			: STD_LOGIC_VECTOR(39 downto 0);
signal Cards_Temp			: STD_LOGIC_VECTOR(39 downto 0); 
SIGNAL Accept			: STD_LOGIC;
signal Card			: STD_LOGIC_VECTOR(3 downto 0);
signal Clk			: STD_LOGIC;
signal HP_Accept			: STD_LOGIC;
signal Reset			: STD_LOGIC;
signal PL_Accept			: STD_LOGIC_VECTOR (n-1 downto 0);
signal Mistake			: STD_LOGIC;
signal Cond			: STD_LOGIC_VECTOR(n downto 0);
signal OR_test			: STD_LOGIC_VECTOR(39 downto 0);
signal Cards_Out			: STD_LOGIC_VECTOR(39 downto 0);
		
		
component Cards_Played
	PORT(
		Card			: IN	STD_LOGIC_VECTOR(3 downto 0);
		Clk			: IN	STD_LOGIC;
		HP_Accept			: IN	STD_LOGIC;
		Reset			: IN	STD_LOGIC;
		PL_Accept			: IN	STD_LOGIC_VECTOR (n-1 downto 0);
		Mistake			: OUT STD_LOGIC;
		Cond			: BUFFER STD_LOGIC_VECTOR(n downto 0);
--		OR_test			: OUT STD_LOGIC_VECTOR(39 downto 0);
		Cards_Out			: BUFFER STD_LOGIC_VECTOR(39 downto 0)
	);

end component;

BEGIN
	
process
		begin 
			Clk <= not Clk;
			wait for 50 ns;
		end process;
		
Top_Module : Cards_Played
	
port map (
	Clk	  => Clk,
	Reset 	  => Reset,
	HP_Accept => HP_Accept,
	PL_Accept => PL_Accept,
	Card	  => Card,			
	Mistake 	 => Mistake,
	Cond	  => Cond,
--	OR_test	  => OR_test,
	Cards_Out	=> Cards_Out
	);
	
	
	
	process
		begin
		 			 	
		 	Reset <= '1';	
			wait for 100 ns;
			
			Reset <= '0'; Card <= "0001"; HP_Accept <= '0' ; PL_Accept <= "011000";
			wait for 200 ns;
			
			Card <= "0010"; HP_Accept <= '0' ; PL_Accept <= "011000";
			wait for 200 ns;
			 
			Card <= "0011";
			wait for 200 ns;
			
			Card <= "0100";HP_Accept <= '0' ; PL_Accept <= "011000";
			wait for 200 ns;
 			
 			Card <= "0101";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
			
			Card <= "1111";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
			 
			Card <= "1010";HP_Accept <= '0' ; PL_Accept <= "011000";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
 			
 			Card <= "1011";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
 			
 			Card <= "0001";HP_Accept <= '0' ; PL_Accept <= "011000";
			wait for 200 ns;
			
			Card <= "0010";
			wait for 200 ns;
			 
			Card <= "0011";
			wait for 200 ns;
			
			Card <= "0100";HP_Accept <= '1' ; PL_Accept <= "000000";
			wait for 200 ns;
 			
 			Card <= "0101";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
			
			Card <= "1111";
			wait for 200 ns;
			
			Card <= "1001";HP_Accept <= '0' ; PL_Accept <= "000000";
			wait for 200 ns;
			 
			Card <= "1010";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
 			
 			Card <= "1011";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
 			
			Card <= "1001";
			wait;
				
	end process;
end tb;