-- MAX+plus II VHDL Template
-- Clearable flipflop with enable
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;


ENTITY Cards_Played IS
generic (n: integer := 6); -- number of players
	PORT
	(
		Card			: IN	STD_LOGIC_VECTOR(3 downto 0);
		Clk			: IN	STD_LOGIC;
		HP_Accept			: IN	STD_LOGIC;
		Reset			: IN	STD_LOGIC;
		PL_Accept			: IN	STD_LOGIC_VECTOR (n-1 downto 0);
		Mistake			: OUT STD_LOGIC;
		Cond			: BUFFER STD_LOGIC_VECTOR(n downto 0);
--		OR_test			: OUT STD_LOGIC_VECTOR(39 downto 0);
		Cards_Out			: BUFFER STD_LOGIC_VECTOR(39 downto 0)
			);
END Cards_Played;

ARCHITECTURE Cards_Played_arch OF Cards_Played IS

--SIGNAL Comp_Zero	: STD_LOGIC_VECTOR(39 downto 0);
SIGNAL OR_Out		: STD_LOGIC_VECTOR(39 downto 0):=(others => '0');
signal Cards_Temp: STD_LOGIC_VECTOR (39 downto 0):=(others => '0'); 
SIGNAL Accept: STD_LOGIC;
	
BEGIN

Cond <= PL_Accept & HP_Accept;

PROCESS (Clk,Reset,Card,Accept,OR_Out,Cards_Out,Cards_Temp)
BEGIN
	if (Reset='1') then
		Cards_Out <= (others => '0');
		OR_Out <= (others => '0');
		Cards_Temp <= (others => '0');
 	elsif (CLK'event and CLK='1') then
		if (Accept = '1')	then  
			OR_Out <= ((X"000000000"& Card) OR Cards_Temp);
--			OR_Test <= OR_Out;
			Cards_Out <= SHL(OR_Out,"100");
			Cards_Temp <= Cards_Out;
		else 
			NULL;
		end if;
		
	end if;				
END PROCESS;	
	
process (Cond)
begin
	if (Cond /= "000000") then
		Accept <= '1';
	else
		Accept <= '0';
	end if;
end process;

END Cards_Played_arch;