-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY Compressed_List IS
PORT(
		Clk : IN STD_LOGIC;
		Reset : IN STD_LOGIC;
		Card: IN STD_LOGIC_VECTOR(3 downto 0);
		Ace: OUT STD_LOGIC_VECTOR(1 downto 0);
		One, Two, Three, Four, Five: OUT STD_LOGIC_VECTOR(3 downto 0);
		Six, Seven, Eight, Nine, Ten: OUT STD_LOGIC_VECTOR(3 downto 0);
		Jack, King, Queen: OUT STD_LOGIC_VECTOR(3 downto 0)

	);
END ;
--two <= shl(one, X"4");

ARCHITECTURE Compressed_List_arch OF Compressed_List IS
SIGNAL Ace_Sig: STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
SIGNAL One_Sig, Two_Sig, Three_Sig, Four_Sig, Five_Sig: STD_LOGIC_VECTOR(3 downto 0):= (others => '0');
SIGNAL Six_Sig, Seven_Sig, Eight_Sig, Nine_Sig, Ten_Sig: STD_LOGIC_VECTOR(3 downto 0):= (others => '0');
SIGNAL Jack_Sig, King_Sig, Queen_Sig: STD_LOGIC_VECTOR(3 downto 0):= (others => '0');

BEGIN

	Compare_Cards: PROCESS (Clk, Reset, Card)
	BEGIN
		if (Reset='1') then
			Ace_Sig <= (others => '0');
			One_Sig <= (others => '0');
			Two_Sig <= (others => '0');
			Three_Sig <= (others => '0');
			Four_Sig <= (others => '0');
			Five_Sig <= (others => '0');
			Six_Sig <= (others => '0');
			Seven_Sig <= (others => '0');
			Eight_Sig <= (others => '0');
			Nine_Sig <= (others => '0');
			Ten_Sig <= (others => '0');
			Jack_Sig <= (others => '0');
			Queen_Sig <= (others => '0');
			King_Sig <= (others => '0');
			
	elsif (CLK'event and CLK='1') then
			case Card is
			when "0000" =>
				Ace_Sig <= Ace_Sig + "01";
			when "0001"=>
				One_Sig	<=  One_Sig + "0001"; 
				
			when "0010"=>
				Two_Sig	<= Two_Sig + "0001";
			
			when "0011"=>
				Three_Sig <= Three_Sig + "0001";
				
			when "0100"=>
				Four_Sig <= Four_Sig + "0001";
				
			when "0101"=>
				Five_Sig <= Five_Sig + "0001";
				
			when "0110"=>
				Six_Sig <= Six_Sig + "0001";
				
			when "0111"=>
				Seven_Sig <= Seven_Sig + "0001";
			when "1000"=>
				Eight_Sig <= Eight_Sig + "0001";
			when "1001"=>
				Nine_Sig <= Nine_Sig + "0001";
			when "1010"=>
				Ten_Sig <= Ten_Sig + "0001";
			when "1011"=>
				Jack_Sig <= Jack_Sig + "0001";
			when "1100"=>
				Queen_Sig <= Queen_Sig+ "0001";
			when "1101"=>
			--	King_Sig <= King_Sig + "0001";
			when others =>
				NULL;
			end case;
		end if;
	END PROCESS;
	Ace <= Ace_Sig;
	One <= One_Sig;
	Two <= Two_Sig;
	Three <= Three_Sig;
	Four <= Four_Sig;
	Five <= Five_Sig;
	Six <= Six_Sig;
	Seven <= Seven_Sig;
	Eight <= Eight_Sig;
	Nine <= Nine_Sig;
	Ten <= Ten_Sig;
	Jack <= Jack_Sig;
	Queen <= Queen_Sig;
	King <= King_Sig;
		
END Compressed_List_arch;