------------------------------------------------------------------
-- Author ---> R.Madhan 
--- Test Bench for Compressed_List.vhd
------------------------------------------------------------------
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity Compressedlist_tb  is
generic (n: integer := 6); -- number of players
end Compressedlist_tb;

architecture tb of Compressedlist_tb is

SIGNAL Ace_Sig			: STD_LOGIC_VECTOR(1 downto 0);
SIGNAL One_Sig, Two_Sig, Three_Sig, Four_Sig, Five_Sig: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL Six_Sig, Seven_Sig, Eight_Sig, Nine_Sig, Ten_Sig: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL Jack_Sig, King_Sig, Queen_Sig: STD_LOGIC_VECTOR(3 downto 0);
signal Clk 		: STD_LOGIC;
signal Reset 		:STD_LOGIC;
signal Card		:STD_LOGIC_VECTOR(3 downto 0);
signal Ace		: STD_LOGIC_VECTOR(1 downto 0);
signal One, Two, Three, Four, Five 	: STD_LOGIC_VECTOR(3 downto 0);
signal Six, Seven, Eight, Nine, Ten	: STD_LOGIC_VECTOR(3 downto 0);
signal Jack, King, Queen				    :STD_LOGIC_VECTOR(3 downto 0);	
signal Mistake :STD_LOGIC := '0';
	
component Compressed_List

	PORT(
		Clk : IN STD_LOGIC;
		Reset : IN STD_LOGIC;
		Card: IN STD_LOGIC_VECTOR(3 downto 0);
		Ace: OUT STD_LOGIC_VECTOR(1 downto 0);
		One, Two, Three, Four, Five: OUT STD_LOGIC_VECTOR(3 downto 0);
		Six, Seven, Eight, Nine, Ten: OUT STD_LOGIC_VECTOR(3 downto 0);
		Jack, King, Queen: OUT STD_LOGIC_VECTOR(3 downto 0)

		);

end component;

BEGIN
	
--process
		--begin 
		--	Clk <= not Clk;
		--	wait for 100 ns;
		--end process;
		
Top_Module : Compressed_List
	
port map (
	Clk	  => Clk,
	Reset 	  => Reset,
	Card	  => Card,			
	Ace 	  => Ace,
	One	  => One,
	Two	  => Two,
	Three	  => Three,
	Four	  => Four,	
	Five	  => Five,
	Six	  => Six,
	Seven	  => Seven,
	Eight	  => Eight,
	Nine	  => Nine,
	Ten	  => Ten,
	Jack	  => Jack,
	King	  => King,
	Queen	  => Queen
	);
	
	
	
	process
		begin
		 			 	
		 	Reset <= '1';	
			wait for 500 ns;
			
			card <= "0000";
			wait for 200 ns;
			
			Reset <= '0'; Card <= "0001"; 
			wait for 200 ns;
			
			Card <= "0010"; 
			wait for 200 ns;
			 
			Card <= "0011";
			wait for 200 ns;
			
			Card <= "0100";
			wait for 200 ns;
 			
 			Card <= "0101";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
			
			Card <= "1111";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
			 
			Card <= "1010";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
 			
 			Card <= "1011";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
 			
 			Card <= "0110";
			wait for 200 ns;
			
			Card <= "0010";
			wait for 200 ns;
			 
			Card <= "0111";
			wait for 200 ns;
			
			Card <= "0100";
			wait for 200 ns;
 			
 			Card <= "0101";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
			
			Card <= "1111";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
			 
			Card <= "1010";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
 			
 			Card <= "1011";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
 			
 			Card <= "0010"; 
			wait for 200 ns;
			 
			Card <= "0011";
			wait for 200 ns;
			
			Card <= "0100";
			wait for 200 ns;
 			
 			Card <= "0101";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
			
			Card <= "1111";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
			 
			Card <= "1010";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
 			
 			Card <= "1011";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
 			
 			Card <= "1101";
			wait for 200 ns;
			
			Card <= "0010";
			wait for 200 ns;
			 
			Card <= "0011";
			wait for 200 ns;
			
			Card <= "0100";
			wait for 200 ns;
 			
 			Card <= "0101";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
			
			Card <= "1111";
			wait for 200 ns;
			
			Card <= "1001";
			wait for 200 ns;
			 
			Card <= "1010";
			wait for 200 ns;
			
			Card <= "1101";
			wait for 200 ns;
 			
 			Card <= "1011";
			wait for 200 ns;
 			
			Card <= "1001";
			wait;
				
	end process;
end tb;