ECE 551 System-on-Chip Design

ECE 551 - System on Chip Design
Fall 2018
Description: This course provides background and hands-on experience with top-down VLSI design flows where custom design techniques are married with HDL synthesis to produce complex digital systems. Topics covered include HDL coding techniques for system-on-chip (SOC) design, standard cell library development and use, synthesis techniques, algorithms for placement and routing, floorplanning, FPGA-based design and prototyping, timing analysis, and power-aware design techniques. Students will gain experience applying top-down VLSI design techniques in the implementation of SOCs, FPGA-based implementations and advanced microprocessors.

 Instrustor:
Dr. Garrett S. Rose
Office: Min Kao 308
Email: garose@utk.edu
Web: web.eecs.utk.edu/~grose4/
Phone: 865-974-3132

Course Syllabus

No Required Textbook:
Suggested Texts:
S. Sutherland, RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design, CreateSpace Independent Publishing, 2017. (ISBN: 978-1546776345)
C. Spear, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, 2012. (ISBN: 978-1461407140)
D. Thomas, Logic Design and Verification Using SystemVerilog, CreateSpace Independent Publishing, 2016. (ISBN: 978-1523364022)

Lectures: MWF 11:15am - 12:05pm, MK406
Office Hours: MW 2:00pm - 3:00pm, MK308

Topics/Lectures:
Lecture # Date Topic Slides
00 8/22 Introduction PDF
01 8/24 Crash Course: VLSI Devices & Circuits PDF
02 8/27 Automated Design Fundamentals PDF
03 8/29 Introduction to Verilog PDF
04 8/31 Introduction to SystemVerilog PDF
HW 1 - DUE AUGUST 31
9/3 HOLIDAY: LABOR DAY
05 9/5 Combinational Logic with SystemVerilog PDF
06 9/7 Testbench Basics for Combinational Logic PDF
07 9/10 State Machine Techniques PDF
08 9/12 Sequential Logic and SystemVerilog Testbenches PDF
09 9/14 The SystemVerilog Program
LAB 1 - DUE SEPTEMBER 14
10 9/17 RTL Verification, Synthesis and Optimization PDF
11 9/19 Automated Layout Generation PDF
9/21 CLASS CANCELED!
9/24 Automated Layout Generation (cont.)
9/26 RTL Optimizations / Retiming (board)
12 9/28 Introducing Bus Communications PDF
HW 2 - DUE SEPTEMBER 28
13 10/1 Bus Standards (AMBA Example) PDF
14 10/3 Simple Bus with SystemVerilog
10/5 HOLIDAY: FALL BREAK
10/8 EXAM REVIEW
10/10 MIDTERM EXAM
10/12 CLASS CANCELED!
15 10/15 Network on Chip Communications
10/17 Network on Chip Communications (cont.)
16 10/19 SystemVerilog Interfaces
PROJECT PROPOSALS - DUE OCTOBER 19
17 10/22 RISC-V Introduction
18 10/24 A Mini-RISC-V Implementation
19 10/26 Mini-RISC-V Assembly Code Development
LAB 2 - DUE OCTOBER 26
20 10/29 RISC-V Environments and TileLink Communication
10/31 Examples: Initiating Mini-RISC-V
11/2 Examples: Assembling Mini-RISC-V Programs
21 11/5 FPGA Prototyping
11/7

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