ECE 551 System-on-Chip Design

ECE 551 - System-on-Chip Design
Fall 2016


Description: This course provides background and hands-on experience with top-down VLSI design flows where custom design techniques are married with HDL synthesis to produce complex digital systems. Topics covered include HDL coding techniques for system-on-chip (SOC) design, standard cell library development and use, synthesis techniques, algorithms for placement and routing, floorplanning, FPGA-based design and prototyping, timing analysis, and power-aware design techniques. Students will gain experience applying top-down VLSI design techniques in the implementation of SOCs, FPGA-based implementations and advanced microprocessors.

Instrustor:
Dr. Garrett S. Rose
Office: Min Kao 308
Email: garose@utk.edu
Web: web.eecs.utk.edu/~grose4/
Phone: 865-974-3132

Course Syllabus

Required Text:
P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-Interscience, 2006. (ISBN: 978-0-471-72092-8)

Lectures: TR 9:40am - 10:55am, MK406

Topics/Lectures:
Lecture # Topic Slides
00 Introduction to VLSI Systems PDF
01 Automated Design Fundamentals
02 VHDL Overview
03 More VHDL Minutiae
04 Structural VHDL
05 Behavioral VHDL Design Practices PDF
06 Behavioral VHDL - State Machines PDF
07 On-Chip Interconnect: Buses (part 1)
08 On-Chip Interconnect: Buses (part 2)
09 On-Chip Interconnect: Network-on-Chip (NoC)
10 SOC Example: SRAD Image Processor
11 PicoBlaze Overview
12 PicoBlaze Assembly Programming w/ Examples
13 PicoBlaze I/O & Interrupt Interface


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