ECE 433/ECE 533 Laboratory
Spring 2018

The labs are designed to give advanced undergraduates and beginning graduate students a working knowledge of CMOS digital integrated circuit technology, circuit design methods, including simulation and physical layout, and design methods for CMOS digital and analog circuit structures. Cadence will be used widely for Circuit simulation. 

Labs and Projects are to be done individually. Please review the lab policy.

           You can access the "Design Rule" through this link.


Lab Open (MK 228):

Monday: 9 am - 5 pm

Tuesday: 9 am - 5 pm

Wednesday: 9 am - 5 pm

Thursday: 9 am - 5 pm

Friday: 9 am - 5 pm

Laboratory classes will start from January 22, 2018.

Lab Hours (MK 228):

Monday: 1 pm - 4 pm

Tuesday: 1pm - 3 pm

Thursday: 1 pm - 4 pm


Office Hours (MK 540):


Lab: The students may work in groups of 2. A TA Checkoff form is required for each student


All due dates are subject to change.

Final Project:

No group work is allowed for the final project. Each student is responsible for their design, report and presentation.

Due: April 24, 2017 (.gds file must be submitted by this deadline)

Designing of a Flip-Flop (T Flip-flop, D Flip-flop, JK flip flop or JK Master Slave flip flop) or 4-bit Counter (Grad Student)
Final reports will be turned into Dr.Islam and students need to prepare for a final presentation given in class. See the attachment for example.

 TA Check-out Form:

For Undergraduate Students: TA CheckOut form for final Project

For Graduate Students: TA CheckOut form for 4-bit Counter design. 

***Attach the TA CheckOut form with final report.


All student will need to plan ahead and start on this project as soon as they feel comfortable with cadence. Students will use the supplied padframe.


Creating layout using LayoutXL: Tutorial

Tutorial for creating layout using standard cell: Tutorial

Tutorial for measuring rise time, fall time and delay: TutorialSubmitting the chip design for fabrication is mandatory for each student