{ @(#)M		1.4  src/bos/usr/sbin/perf/pmapi/libpmapi/POWER4.evs, pmapi, bos51C, c2001_41B1 10/6/01 14:55:52
{ IBM_PROLOG_BEGIN_TAG 
{ This is an automatically generated prolog. 
{  
{ bos51C src/bos/usr/sbin/perf/pmapi/libpmapi/POWER4.evs 1.4 
{  
{ Licensed Materials - Property of IBM 
{  
{ (C) COPYRIGHT International Business Machines Corp. 2001 
{ All Rights Reserved 
{  
{ US Government Users Restricted Rights - Use, duplication or 
{ disclosure restricted by GSA ADP Schedule Contract with IBM Corp. 
{  
{ IBM_PROLOG_END_TAG 
POWER4,95,93,85,86,95,94,85,87

{ counter 1 }
#0,u,g,PM_BIQ_IDU_FULL_CYC,Cycles BIQ or IDU full
##0224,0824
Cycles BIQ or IDU full
#1,u,g,PM_BRQ_FULL_CYC,Cycles branch queue full
##0105,0605
Cycles branch queue full
#2,u,g,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full
##0104,0604
Cycles CR logical operation mapper full
#3,u,g,PM_DC_PREF_L2_CLONE_L3,L2 prefetch cloned with L3
##0C27
L2 prefetch cloned with L3
#4,u,g,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated
##0907
D cache new prefetch stream allocated
#5,u,g,PM_DSLB_MISS,Data SLB misses
##0905
Data SLB misses
#6,u,g,PM_DTLB_MISS,Data TLB misses
##0904
Data TLB misses
#7,u,g,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full
##0101,0601
Cycles FPR mapper full
#8,u,g,PM_FPU0_ALL,FPU0 executed add, mult, sub, cmp or sel instruction
##0003
FPU0 executed add, mult, sub, cmp or sel instruction
#9,u,g,PM_FPU0_DENORM,FPU0 received denormalized data
##0020
FPU0 received denormalized data
#10,u,g,PM_FPU0_FDIV,FPU0 executed FDIV instruction
##0000
FPU0 executed FDIV instruction
#11,u,g,PM_FPU0_FMA,FPU0 executed multiply-add instruction
##0001
FPU0 executed multiply-add instruction
#12,u,g,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction
##0002
FPU0 executed FSQRT instruction
#13,u,g,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full
##0103,0603
Cycles FPU0 issue queue full
#14,u,g,PM_FPU0_SINGLE,FPU0 executed single precision instruction
##0023
FPU0 executed single precision instruction
#15,u,g,PM_FPU0_STALL3,FPU0 stalled in pipe3
##0021
FPU0 stalled in pipe3
#16,u,g,PM_FPU0_STF,FPU0 executed store instruction
##0022
FPU0 executed store instruction
#17,u,g,PM_FPU1_ALL,FPU1 executed add, mult, sub, cmp or sel instruction
##0007
FPU1 executed add, mult, sub, cmp or sel instruction
#18,u,g,PM_FPU1_DENORM,FPU1 received denormalized data
##0024
FPU1 received denormalized data
#19,u,g,PM_FPU1_FDIV,FPU1 executed FDIV instruction
##0004
FPU1 executed FDIV instruction
#20,u,g,PM_FPU1_FMA,FPU1 executed multiply-add instruction
##0005
FPU1 executed multiply-add instruction
#21,u,g,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction
##0006
FPU1 executed FSQRT instruction
#22,u,g,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full
##0107,0607
Cycles FPU1 issue queue full
#23,u,g,PM_FPU1_SINGLE,FPU1 executed single precision instruction
##0027
FPU1 executed single precision instruction
#24,u,g,PM_FPU1_STALL3,FPU1 stalled in pipe3
##0025
FPU1 stalled in pipe3
#25,u,g,PM_FPU1_STF,FPU1 executed store instruction
##0026
FPU1 executed store instruction
#26,u,g,PM_GCT_FULL_CYC,Cycles GCT full
##0100,0600
Cycles GCT full
#27,u,g,PM_GRP_DISP_REJECT,Group dispatch rejected
##0124,0624
Group dispatch rejected
#28,u,g,PM_GRP_DISP_VALID,Group dispatch valid
##0123,0623
Group dispatch valid
#29,u,g,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch buffer
##0225,0825
Instruction prefetched installed in prefetch buffer
#30,u,g,PM_IC_PREF_REQ,Instruction prefetch requests
##0226,0826
Instruction prefetch requests
#31,u,g,PM_IERAT_XLATE_WR,Translation written to ierat
##0227,0827
Translation written to ierat
#32,u,g,PM_INST_DISP,Instructions dispatched
##0121,0621
Instructions dispatched
#33,u,g,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched
##0223,0823
Cycles at least 1 instruction fetched
#34,u,g,PM_ISLB_MISS,Instruction SLB misses
##0901
Instruction SLB misses
#35,u,g,PM_ITLB_MISS,Instruction TLB misses
##0900
Instruction TLB misses
#36,u,g,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid
##0C64
L1 reload data source valid
#37,u,g,PM_L2SA_MOD_INV,L2 slice A transition from modified to invalid
##4007
L2 slice A transition from modified to invalid
#38,u,g,PM_L2SA_MOD_TAG,L2 slice A transition from modified to tagged
##4006
L2 slice A transition from modified to tagged
#39,u,g,PM_L2SA_SHR_INV,L2 slice A transition from shared to invalid
##4005
L2 slice A transition from shared to invalid
#40,u,g,PM_L2SA_SHR_MOD,L2 slice A transition from shared to modified
##4004
L2 slice A transition from shared to modified
#41,u,g,PM_L2SB_MOD_INV,L2 slice B transition from modified to invalid
##4023
L2 slice B transition from modified to invalid
#42,u,g,PM_L2SB_MOD_TAG,L2 slice B transition from modified to tagged
##4022
L2 slice B transition from modified to tagged
#43,u,g,PM_L2SB_SHR_INV,L2 slice B transition from shared to invalid
##4021
L2 slice B transition from shared to invalid
#44,u,g,PM_L2SB_SHR_MOD,L2 slice B transition from shared to modified
##4020
L2 slice B transition from shared to modified
#45,u,g,PM_L2SC_MOD_INV,L2 slice C transition from modified to invalid
##4027
L2 slice C transition from modified to invalid
#46,u,g,PM_L2SC_MOD_TAG,L2 slice C transition from modified to tagged
##4026
L2 slice C transition from modified to tagged
#47,u,g,PM_L2SC_SHR_INV,L2 slice C transition from shared to invalid
##4025
L2 slice C transition from shared to invalid
#48,u,g,PM_L2SC_SHR_MOD,L2 slice C transition from shared to modified
##4024
L2 slice C transition from shared to modified
#49,u,g,PM_L3B0_DIR_MIS,L3 bank 0 directory misses
##4001
L3 bank 0 directory misses
#50,u,g,PM_L3B0_DIR_REF,L3 bank 0 directory references
##4000
L3 bank 0 directory references
#51,u,g,PM_L3B1_DIR_MIS,L3 bank 1 directory misses
##4003
L3 bank 1 directory misses
#52,u,g,PM_L3B1_DIR_REF,L3 bank 1 directory references
##4002
L3 bank 1 directory references
#53,u,g,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full
##0106,0606
Cycles LR/CTR mapper full
#54,u,g,PM_LSU0_DERAT_MISS,LSU0 DERAT misses
##0902
LSU0 DERAT misses
#55,u,g,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes
##0C02
LSU0 LRQ flushes
#56,u,g,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes
##0C03
LSU0 SRQ flushes
#57,u,g,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes
##0C00
LSU0 unaligned load flushes
#58,u,g,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes
##0C01
LSU0 unaligned store flushes
#59,u,g,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded
##0C20
LSU0 SRQ store forwarded
#60,u,g,PM_LSU1_DERAT_MISS,LSU1 DERAT misses
##0906
LSU1 DERAT misses
#61,u,g,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes
##0C06
LSU1 LRQ flushes
#62,u,g,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes
##0C07
LSU1 SRQ flushes
#63,u,g,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes
##0C04
LSU1 unaligned load flushes
#64,u,g,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes
##0C05
LSU1 unaligned store flushes
#65,u,g,PM_LSU1_SRQ_STFWD,LSU0 SRQ store forwarded
##0C24
LSU0 SRQ store forwarded
#66,u,g,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full
##0927
Cycles LMQ full
#67,u,g,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges
##0926
LMQ LHR merges
#68,u,g,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated
##0C26
LRQ slot 0 allocated
#69,u,g,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid
##0C22
LRQ slot 0 valid
#70,u,g,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated
##0C25
SRQ slot 0 allocated
#71,u,g,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid
##0C21
SRQ slot 0 valid
#72,u,g,PM_MRK_IMR_RELOAD,Marked IMR reloaded
##0922
Marked IMR reloaded
#73,u,g,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses
##0920
LSU0 L1 D cache load misses
#74,u,g,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses
##0924
LSU1 L1 D cache load misses
#75,u,g,PM_MRK_STCX_FAIL,Marked STCX failed
##0925
Marked STCX failed
#76,u,g,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses
##0923
Marked L1 D cache store misses
#77,u,g,PM_SNOOP_TLBIE,Snoop TLBIE
##0903
Snoop TLBIE
#78,u,g,PM_STCX_FAIL,STCX failed
##0921
STCX failed
#79,u,g,PM_ST_MISS_L1,L1 D cache store misses
##0C23
L1 D cache store misses
#80,u,g,PM_XER_MAP_FULL_CYC,Cycles XER mapper full
##0102,0602
Cycles XER mapper full
#81,u,g,PM_CYC,Processor cycles
##800F
Processor cycles
#82,u,g,PM_DATA_FROM_L3,Data loaded from L3
##8C66
Data loaded from L3
#83,u,g,PM_FPU_DENORM,FPU received denormalized data
##8020
FPU received denormalized data
#84,u,g,PM_FPU_FDIV,FPU executed FDIV instruction
##8000
FPU executed FDIV instruction
#85,u,g,PM_GCT_EMPTY_CYC,Cycles GCT empty
##8004
Cycles GCT empty
#86,u,g,PM_INST_CMPL,Instructions completed
##8001
Instructions completed
#87,u,g,PM_INST_FROM_MEM,Instruction fetched from memory
##8227
Instruction fetched from memory
#88,u,g,PM_LSU_FLUSH_ULD,LRQ unaligned load flushes
##8C00
LRQ unaligned load flushes
#89,u,g,PM_LSU_SRQ_STFWD,SRQ store forwarded
##0C24
SRQ store forwarded
#90,u,g,PM_MRK_DATA_FROM_L3,Marked data loaded from L3
##8C76
Marked data loaded from L3
#91,u,g,PM_MRK_GRP_DISP,Marked group dispatched
##8002
Marked group dispatched
#92,u,g,PM_MRK_LD_MISS_L1,Marked L1 D cache load misses
##8920
Marked L1 D cache load misses
#93,u,g,PM_MRK_ST_CMPL,Marked store instruction completed
##8003
Marked store instruction completed
#94,u,g,PM_RUN_CYC,Run cycles
##8005
Run cycles
$$$$

{ counter 2 }
#0,u,g,PM_BIQ_IDU_FULL_CYC,Cycles BIQ or IDU full
##0224,0824
Cycles BIQ or IDU full
#1,u,g,PM_BRQ_FULL_CYC,Cycles branch queue full
##0105,0605
Cycles branch queue full
#2,u,g,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full
##0104,0604
Cycles CR logical operation mapper full
#3,u,g,PM_DC_PREF_L2_CLONE_L3,L2 prefetch cloned with L3
##0C27
L2 prefetch cloned with L3
#4,u,g,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated
##0907
D cache new prefetch stream allocated
#5,u,g,PM_DSLB_MISS,Data SLB misses
##0905
Data SLB misses
#6,u,g,PM_DTLB_MISS,Data TLB misses
##0904
Data TLB misses
#7,u,g,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full
##0101,0601
Cycles FPR mapper full
#8,u,g,PM_FPU0_ALL,FPU0 executed add, mult, sub, cmp or sel instruction
##0003
FPU0 executed add, mult, sub, cmp or sel instruction
#9,u,g,PM_FPU0_DENORM,FPU0 received denormalized data
##0020
FPU0 received denormalized data
#10,u,g,PM_FPU0_FDIV,FPU0 executed FDIV instruction
##0000
FPU0 executed FDIV instruction
#11,u,g,PM_FPU0_FMA,FPU0 executed multiply-add instruction
##0001
FPU0 executed multiply-add instruction
#12,u,g,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction
##0002
FPU0 executed FSQRT instruction
#13,u,g,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full
##0103,0603
Cycles FPU0 issue queue full
#14,u,g,PM_FPU0_SINGLE,FPU0 executed single precision instruction
##0023
FPU0 executed single precision instruction
#15,u,g,PM_FPU0_STALL3,FPU0 stalled in pipe3
##0021
FPU0 stalled in pipe3
#16,u,g,PM_FPU0_STF,FPU0 executed store instruction
##0022
FPU0 executed store instruction
#17,u,g,PM_FPU1_ALL,FPU1 executed add, mult, sub, cmp or sel instruction
##0007
FPU1 executed add, mult, sub, cmp or sel instruction
#18,u,g,PM_FPU1_DENORM,FPU1 received denormalized data
##0024
FPU1 received denormalized data
#19,u,g,PM_FPU1_FDIV,FPU1 executed FDIV instruction
##0004
FPU1 executed FDIV instruction
#20,u,g,PM_FPU1_FMA,FPU1 executed multiply-add instruction
##0005
FPU1 executed multiply-add instruction
#21,u,g,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction
##0006
FPU1 executed FSQRT instruction
#22,u,g,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full
##0107,0607
Cycles FPU1 issue queue full
#23,u,g,PM_FPU1_SINGLE,FPU1 executed single precision instruction
##0027
FPU1 executed single precision instruction
#24,u,g,PM_FPU1_STALL3,FPU1 stalled in pipe3
##0025
FPU1 stalled in pipe3
#25,u,g,PM_FPU1_STF,FPU1 executed store instruction
##0026
FPU1 executed store instruction
#26,u,g,PM_GCT_FULL_CYC,Cycles GCT full
##0100,0600
Cycles GCT full
#27,u,g,PM_GRP_DISP_REJECT,Group dispatch rejected
##0124,0624
Group dispatch rejected
#28,u,g,PM_GRP_DISP_VALID,Group dispatch valid
##0123,0623
Group dispatch valid
#29,u,g,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch buffer
##0225,0825
Instruction prefetched installed in prefetch buffer
#30,u,g,PM_IC_PREF_REQ,Instruction prefetch requests
##0226,0826
Instruction prefetch requests
#31,u,g,PM_IERAT_XLATE_WR,Translation written to ierat
##0227,0827
Translation written to ierat
#32,u,g,PM_INST_DISP,Instructions dispatched
##0121,0621
Instructions dispatched
#33,u,g,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched
##0223,0823
Cycles at least 1 instruction fetched
#34,u,g,PM_ISLB_MISS,Instruction SLB misses
##0901
Instruction SLB misses
#35,u,g,PM_ITLB_MISS,Instruction TLB misses
##0900
Instruction TLB misses
#36,u,g,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid
##0C64
L1 reload data source valid
#37,u,g,PM_L2SA_MOD_INV,L2 slice A transition from modified to invalid
##4007
L2 slice A transition from modified to invalid
#38,u,g,PM_L2SA_MOD_TAG,L2 slice A transition from modified to tagged
##4006
L2 slice A transition from modified to tagged
#39,u,g,PM_L2SA_SHR_INV,L2 slice A transition from shared to invalid
##4005
L2 slice A transition from shared to invalid
#40,u,g,PM_L2SA_SHR_MOD,L2 slice A transition from shared to modified
##4004
L2 slice A transition from shared to modified
#41,u,g,PM_L2SB_MOD_INV,L2 slice B transition from modified to invalid
##4023
L2 slice B transition from modified to invalid
#42,u,g,PM_L2SB_MOD_TAG,L2 slice B transition from modified to tagged
##4022
L2 slice B transition from modified to tagged
#43,u,g,PM_L2SB_SHR_INV,L2 slice B transition from shared to invalid
##4021
L2 slice B transition from shared to invalid
#44,u,g,PM_L2SB_SHR_MOD,L2 slice B transition from shared to modified
##4020
L2 slice B transition from shared to modified
#45,u,g,PM_L2SC_MOD_INV,L2 slice C transition from modified to invalid
##4027
L2 slice C transition from modified to invalid
#46,u,g,PM_L2SC_MOD_TAG,L2 slice C transition from modified to tagged
##4026
L2 slice C transition from modified to tagged
#47,u,g,PM_L2SC_SHR_INV,L2 slice C transition from shared to invalid
##4025
L2 slice C transition from shared to invalid
#48,u,g,PM_L2SC_SHR_MOD,L2 slice C transition from shared to modified
##4024
L2 slice C transition from shared to modified
#49,u,g,PM_L3B0_DIR_MIS,L3 bank 0 directory misses
##4001
L3 bank 0 directory misses
#50,u,g,PM_L3B0_DIR_REF,L3 bank 0 directory references
##4000
L3 bank 0 directory references
#51,u,g,PM_L3B1_DIR_MIS,L3 bank 1 directory misses
##4003
L3 bank 1 directory misses
#52,u,g,PM_L3B1_DIR_REF,L3 bank 1 directory references
##4002
L3 bank 1 directory references
#53,u,g,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full
##0106,0606
Cycles LR/CTR mapper full
#54,u,g,PM_LSU0_DERAT_MISS,LSU0 DERAT misses
##0902
LSU0 DERAT misses
#55,u,g,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes
##0C02
LSU0 LRQ flushes
#56,u,g,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes
##0C03
LSU0 SRQ flushes
#57,u,g,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes
##0C00
LSU0 unaligned load flushes
#58,u,g,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes
##0C01
LSU0 unaligned store flushes
#59,u,g,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded
##0C20
LSU0 SRQ store forwarded
#60,u,g,PM_LSU1_DERAT_MISS,LSU1 DERAT misses
##0906
LSU1 DERAT misses
#61,u,g,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes
##0C06
LSU1 LRQ flushes
#62,u,g,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes
##0C07
LSU1 SRQ flushes
#63,u,g,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes
##0C04
LSU1 unaligned load flushes
#64,u,g,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes
##0C05
LSU1 unaligned store flushes
#65,u,g,PM_LSU1_SRQ_STFWD,LSU0 SRQ store forwarded
##0C24
LSU0 SRQ store forwarded
#66,u,g,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full
##0927
Cycles LMQ full
#67,u,g,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges
##0926
LMQ LHR merges
#68,u,g,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated
##0C26
LRQ slot 0 allocated
#69,u,g,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid
##0C22
LRQ slot 0 valid
#70,u,g,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated
##0C25
SRQ slot 0 allocated
#71,u,g,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid
##0C21
SRQ slot 0 valid
#72,u,g,PM_MRK_IMR_RELOAD,Marked IMR reloaded
##0922
Marked IMR reloaded
#73,u,g,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses
##0920
LSU0 L1 D cache load misses
#74,u,g,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses
##0924
LSU1 L1 D cache load misses
#75,u,g,PM_MRK_STCX_FAIL,Marked STCX failed
##0925
Marked STCX failed
#76,u,g,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses
##0923
Marked L1 D cache store misses
#77,u,g,PM_SNOOP_TLBIE,Snoop TLBIE
##0903
Snoop TLBIE
#78,u,g,PM_STCX_FAIL,STCX failed
##0921
STCX failed
#79,u,g,PM_ST_MISS_L1,L1 D cache store misses
##0C23
L1 D cache store misses
#80,u,g,PM_XER_MAP_FULL_CYC,Cycles XER mapper full
##0102,0602
Cycles XER mapper full
#81,u,g,PM_CYC,Processor cycles
##800F
Processor cycles
#82,u,g,PM_DATA_FROM_MEM,Data loaded from memory
##8C66
Data loaded from memory
#83,u,g,PM_FPU_FMA,FPU executed multiply-add instruction
##8000
FPU executed multiply-add instruction
#84,u,g,PM_FPU_STALL3,FPU stalled in pipe3
##8020
FPU stalled in pipe3
#85,u,g,PM_GRP_DISP,Group dispatches
##8004
Group dispatches
#86,u,g,PM_INST_FROM_L25_L275,Instruction fetched from L2.5/L2.75
##8227
Instruction fetched from L2.5/L2.75
#87,u,g,PM_LSU_FLUSH_UST,SRQ unaligned store flushes
##8C00
SRQ unaligned store flushes
#88,u,g,PM_LSU_LMQ_SRQ_EMPTY_CYC,Cycles LMQ and LMQ empty
##8002
Cycles LMQ and LMQ empty
#89,u,g,PM_MRK_BRU_FIN,Marked instruction BRU processing finished
##8005
Marked instruction BRU processing finished
#90,u,g,PM_MRK_DATA_FROM_MEM,Marked data loaded from memory
##8C76
Marked data loaded from memory
#91,u,G,PM_THRESH_TIMEO,Threshold timeout
##8003
Threshold timeout
#92,u,g,PM_WORK_HELD,Work held
##8001
Work held
$$$$

{ counter 3 }
#0,u,g,PM_1INST_CLB_CYC,Cycles 1 instruction in CLB
##0450
Cycles 1 instruction in CLB
#1,u,g,PM_2INST_CLB_CYC,Cycles 2 instructions in CLB
##0451
Cycles 2 instructions in CLB
#2,u,g,PM_3INST_CLB_CYC,Cycles 3 instructions in CLB
##0452
Cycles 3 instructions in CLB
#3,u,g,PM_4INST_CLB_CYC,Cycles 4 instructions in CLB
##0453
Cycles 4 instructions in CLB
#4,u,g,PM_5INST_CLB_CYC,Cycles 5 instructions in CLB
##0454
Cycles 5 instructions in CLB
#5,u,g,PM_6INST_CLB_CYC,Cycles 6 instructions in CLB
##0455
Cycles 6 instructions in CLB
#6,u,g,PM_7INST_CLB_CYC,Cycles 7 instructions in CLB
##0456
Cycles 7 instructions in CLB
#7,u,g,PM_8INST_CLB_CYC,Cycles 8 instructions in CLB
##0457
Cycles 8 instructions in CLB
#8,u,g,PM_BR_ISSUED,Branches issued
##0230,0830
Branches issued
#9,u,g,PM_BR_MPRED_CR,Branch mispredictions due CR bit setting
##0231,0831
Branch mispredictions due CR bit setting
#10,u,g,PM_BR_MPRED_TA,Branch mispredictions due to target address
##0232,0832
Branch mispredictions due to target address
#11,u,g,PM_CRQ_FULL_CYC,Cycles CR issue queue full
##0111,0611
Cycles CR issue queue full
#12,u,g,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks
##0936
Cycles doing data tablewalks
#13,u,g,PM_DC_INV_L2,L1 D cache entries invalidated from L2
##0C17
L1 D cache entries invalidated from L2
#14,u,g,PM_DC_PREF_OUT_STREAMS,Out of prefetch streams
##0C36
Out of prefetch streams
#15,u,g,PM_EE_OFF,Cycles MSR(EE) bit off
##0133,0633
Cycles MSR(EE) bit off
#16,u,g,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending
##0137,0637
Cycles MSR(EE) bit off and external interrupt pending
#17,u,g,PM_FAB_CMD_ISSUED,Fabric command issued
##4016
Fabric command issued
#18,u,g,PM_FAB_CMD_RETRIED,Fabric command retried
##4017
Fabric command retried
#19,u,g,PM_LSU0_LDF,LSU0 executed Floating Point load instruction
##0930
LSU0 executed Floating Point load instruction
#20,u,g,PM_LSU1_LDF,LSU1 executed Floating Point load instruction
##0934
LSU1 executed Floating Point load instruction
#21,u,g,PM_FPU0_FEST,FPU0 executed FEST instruction
##0012
FPU0 executed FEST instruction
#22,u,g,PM_FPU0_FIN,FPU0 produced a result
##0013
FPU0 produced a result
#23,u,g,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions
##0010
FPU0 executed FMOV or FEST instructions
#24,u,g,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction
##0030
FPU0 executed FPSCR instruction
#25,u,g,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions
##0011
FPU0 executed FRSP or FCONV instructions
#26,u,g,PM_FPU1_FEST,FPU1 executed FEST instruction
##0016
FPU1 executed FEST instruction
#27,u,g,PM_FPU1_FIN,FPU1 produced a result
##0017
FPU1 produced a result
#28,u,g,PM_FPU1_FMOV_FEST,FPU0 executing FMOV or FEST instructions
##0014
FPU0 executing FMOV or FEST instructions
#29,u,g,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions
##0015
FPU1 executed FRSP or FCONV instructions
#30,u,g,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full
##0110,0114,0610,0614
Cycles FXU0/LS0 queue full
#31,u,g,PM_FXU0_FIN,FXU0 produced a result
##0132,0632
FXU0 produced a result
#32,u,g,PM_FXU1_FIN,FXU1 produced a result
##0136,0636
FXU1 produced a result
#33,u,g,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full
##0135,0635
Cycles GPR mapper full
#34,u,g,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard
##0131,0631
Cycles group dispatch blocked by scoreboard
#35,u,g,PM_L1_PREF,L1 cache data prefetches
##0C35
L1 cache data prefetches
#36,u,g,PM_L1_WRITE_CYC,Cycles writing to instruction L1
##0233,0833
Cycles writing to instruction L1
#37,u,g,PM_L2SA_ST_HIT,L2 slice A store hits
##4011
L2 slice A store hits
#38,u,g,PM_L2SA_ST_REQ,L2 slice A store requests
##4010
L2 slice A store requests
#39,u,g,PM_L2SB_ST_HIT,L2 slice B store hits
##4013
L2 slice B store hits
#40,u,g,PM_L2SB_ST_REQ,L2 slice B store requests
##4012
L2 slice B store requests
#41,u,g,PM_L2SC_ST_HIT,L2 slice C store hits
##4015
L2 slice C store hits
#42,u,g,PM_L2SC_ST_REQ,L2 slice C store requests
##4014
L2 slice C store requests
#43,u,g,PM_L2_PREF,L2 cache prefetches
##0C34
L2 cache prefetches
#44,u,g,PM_LARX_LSU0,Larx executed on LSU0
##0C73
Larx executed on LSU0
#45,u,g,PM_LARX_LSU1,Larx executed on LSU1
##0C77
Larx executed on LSU1
#46,u,g,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses
##0C12
LSU0 L1 D cache load misses
#47,u,g,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses
##0C16
LSU1 L1 D cache load misses
#48,u,g,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references
##0C10
LSU0 L1 D cache load references
#49,u,g,PM_LD_REF_L1_LSU1,LSU1 L1 D cache load references
##0C14
LSU1 L1 D cache load references
#50,u,g,PM_LSU0_BUSY,LSU0 busy
##0C33
LSU0 busy
#51,u,g,PM_LSU1_BUSY,LSU1 busy
##0C37
LSU1 busy
#52,u,g,PM_LSU_LMQ_S0_ALLOC,LMQ slot 0 allocated
##0935
LMQ slot 0 allocated
#53,u,g,PM_LSU_LMQ_S0_VALID,LMQ slot 0 valid
##0931
LMQ slot 0 valid
#54,u,g,PM_LSU_LRQ_FULL_CYC,Cycles LRQ full
##0112,0612
Cycles LRQ full
#55,u,g,PM_LSU_SRQ_FULL_CYC,Cycles SRQ full
##0113,0613
Cycles SRQ full
#56,u,g,PM_LSU_SRQ_SYNC_CYC,SRQ sync duration
##0932
SRQ sync duration
#57,u,g,PM_MRK_L1_RELOAD_VALID,Marked L1 reload data source valid
##0C74
Marked L1 reload data source valid
#58,u,g,PM_MRK_LSU0_FLUSH_LRQ,LSU0 marked LRQ flushes
##0912
LSU0 marked LRQ flushes
#59,u,g,PM_MRK_LSU0_FLUSH_SRQ,LSU0 marked SRQ flushes
##0913
LSU0 marked SRQ flushes
#60,u,g,PM_MRK_LSU0_FLUSH_ULD,LSU0 marked unaligned load flushes
##0911
LSU0 marked unaligned load flushes
#61,u,g,PM_MRK_LSU0_FLUSH_UST,LSU0 marked unaligned store flushes
##0910
LSU0 marked unaligned store flushes
#62,u,g,PM_MRK_LSU0_INST_FIN,LSU0 finished a marked instruction
##0C31
LSU0 finished a marked instruction
#63,u,g,PM_MRK_LSU1_FLUSH_LRQ,LSU1 marked LRQ flushes
##0916
LSU1 marked LRQ flushes
#64,u,g,PM_MRK_LSU1_FLUSH_SRQ,LSU1 marked SRQ flushes
##0917
LSU1 marked SRQ flushes
#65,u,g,PM_MRK_LSU1_FLUSH_ULD,LSU1 marked unaligned load flushes
##0915
LSU1 marked unaligned load flushes
#66,u,g,PM_MRK_LSU1_FLUSH_UST,LSU1 marked unaligned store flushes
##0914
LSU1 marked unaligned store flushes
#67,u,g,PM_MRK_LSU1_INST_FIN,LSU1 finished a marked instruction
##0C32
LSU1 finished a marked instruction
#68,u,g,PM_MRK_LSU_SRQ_INST_VALID,Marked instruction valid in SRQ
##0933
Marked instruction valid in SRQ
#69,u,g,PM_STCX_PASS,Stcx passes
##0C75
Stcx passes
#70,u,g,PM_ST_MISS_L1,L1 D cache store misses
##0C13
L1 D cache store misses
#71,u,g,PM_ST_REF_L1_LSU0,LSU0 L1 D cache store references
##0C11
LSU0 L1 D cache store references
#72,u,g,PM_ST_REF_L1_LSU1,LSU1 L1 D cache store references
##0C15
LSU1 L1 D cache store references
#73,u,g,PM_CYC,Processor cycles
##800F
Processor cycles
#74,u,g,PM_DATA_FROM_L35,Data loaded from L3.5
##8C66
Data loaded from L3.5
#75,u,g,PM_FPU_FEST,FPU executed FEST instruction
##8010
FPU executed FEST instruction
#76,u,g,PM_FXU_FIN,FXU produced a result
##8130
FXU produced a result
#77,u,g,PM_FXU_FIN,FXU produced a result
##8630
FXU produced a result
#78,u,g,PM_INST_FROM_L2,Instructions fetched from L2
##8227
Instructions fetched from L2
#79,u,g,PM_LD_MISS_L1,L1 D cache load misses
##8C10
L1 D cache load misses
#80,u,g,PM_MRK_DATA_FROM_L35,Marked data loaded from L3.5
##8C76
Marked data loaded from L3.5
#81,u,g,PM_MRK_LSU_FLUSH_LRQ,Marked LRQ flushes
##8910
Marked LRQ flushes
#82,u,g,PM_MRK_ST_CMPL_INT,Marked store completed with intervention
##8003
Marked store completed with intervention
#83,u,g,PM_STOP_COMPLETION,Completion stopped
##8001
Completion stopped
#84,u,g,PM_HV_CYC,Hypervisor Cycles
##8004
Hypervisor Cycles
$$$$

{ counter 4 }
#0,u,g,PM_1INST_CLB_CYC,Cycles 1 instruction in CLB
##0450
Cycles 1 instruction in CLB
#1,u,g,PM_2INST_CLB_CYC,Cycles 2 instructions in CLB
##0451
Cycles 2 instructions in CLB
#2,u,g,PM_3INST_CLB_CYC,Cycles 3 instructions in CLB
##0452
Cycles 3 instructions in CLB
#3,u,g,PM_4INST_CLB_CYC,Cycles 4 instructions in CLB
##0453
Cycles 4 instructions in CLB
#4,u,g,PM_5INST_CLB_CYC,Cycles 5 instructions in CLB
##0454
Cycles 5 instructions in CLB
#5,u,g,PM_6INST_CLB_CYC,Cycles 6 instructions in CLB
##0455
Cycles 6 instructions in CLB
#6,u,g,PM_7INST_CLB_CYC,Cycles 7 instructions in CLB
##0456
Cycles 7 instructions in CLB
#7,u,g,PM_8INST_CLB_CYC,Cycles 8 instructions in CLB
##0457
Cycles 8 instructions in CLB
#8,u,g,PM_BR_ISSUED,Branches issued
##0230,0830
Branches issued
#9,u,g,PM_BR_MPRED_CR,Branch mispredictions due CR bit setting
##0231,0831
Branch mispredictions due CR bit setting
#10,u,g,PM_BR_MPRED_TA,Branch mispredictions due to target address
##0232,0832
Branch mispredictions due to target address
#11,u,g,PM_CRQ_FULL_CYC,Cycles CR issue queue full
##0111,0611
Cycles CR issue queue full
#12,u,g,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks
##0936
Cycles doing data tablewalks
#13,u,g,PM_DC_INV_L2,L1 D cache entries invalidated from L2
##0C17
L1 D cache entries invalidated from L2
#14,u,g,PM_DC_PREF_OUT_STREAMS,Out of prefetch streams
##0C36
Out of prefetch streams
#15,u,g,PM_EE_OFF,Cycles MSR(EE) bit off
##0133,0633
Cycles MSR(EE) bit off
#16,u,g,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending
##0137,0637
Cycles MSR(EE) bit off and external interrupt pending
#17,u,g,PM_FAB_CMD_ISSUED,Fabric command issued
##4016
Fabric command issued
#18,u,g,PM_FAB_CMD_RETRIED,Fabric command retried
##4017
Fabric command retried
#19,u,g,PM_LSU0_LDF,LSU0 executed Floating Point load instruction
##0930
LSU0 executed Floating Point load instruction
#20,u,g,PM_LSU1_LDF,LSU1 executed Floating Point load instruction
##0934
LSU1 executed Floating Point load instruction
#21,u,g,PM_FPU0_FEST,FPU0 executed FEST instruction
##0012
FPU0 executed FEST instruction
#22,u,g,PM_FPU0_FIN,FPU0 produced a result
##0013
FPU0 produced a result
#23,u,g,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions
##0010
FPU0 executed FMOV or FEST instructions
#24,u,g,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction
##0030
FPU0 executed FPSCR instruction
#25,u,g,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions
##0011
FPU0 executed FRSP or FCONV instructions
#26,u,g,PM_FPU1_FEST,FPU1 executed FEST instruction
##0016
FPU1 executed FEST instruction
#27,u,g,PM_FPU1_FIN,FPU1 produced a result
##0017
FPU1 produced a result
#28,u,g,PM_FPU1_FMOV_FEST,FPU0 executing FMOV or FEST instructions
##0014
FPU0 executing FMOV or FEST instructions
#29,u,g,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions
##0015
FPU1 executed FRSP or FCONV instructions
#30,u,g,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full
##0110,0114,0610,0614
Cycles FXU0/LS0 queue full
#31,u,g,PM_FXU0_FIN,FXU0 produced a result
##0132,0632
FXU0 produced a result
#32,u,g,PM_FXU1_FIN,FXU1 produced a result
##0136,0636
FXU1 produced a result
#33,u,g,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full
##0135,0635
Cycles GPR mapper full
#34,u,g,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard
##0131,0631
Cycles group dispatch blocked by scoreboard
#35,u,g,PM_L1_PREF,L1 cache data prefetches
##0C35
L1 cache data prefetches
#36,u,g,PM_L1_WRITE_CYC,Cycles writing to instruction L1
##0233,0833
Cycles writing to instruction L1
#37,u,g,PM_L2SA_ST_HIT,L2 slice A store hits
##4011
L2 slice A store hits
#38,u,g,PM_L2SA_ST_REQ,L2 slice A store requests
##4010
L2 slice A store requests
#39,u,g,PM_L2SB_ST_HIT,L2 slice B store hits
##4013
L2 slice B store hits
#40,u,g,PM_L2SB_ST_REQ,L2 slice B store requests
##4012
L2 slice B store requests
#41,u,g,PM_L2SC_ST_HIT,L2 slice C store hits
##4015
L2 slice C store hits
#42,u,g,PM_L2SC_ST_REQ,L2 slice C store requests
##4014
L2 slice C store requests
#43,u,g,PM_L2_PREF,L2 cache prefetches
##0C34
L2 cache prefetches
#44,u,g,PM_LARX_LSU0,Larx executed on LSU0
##0C73
Larx executed on LSU0
#45,u,g,PM_LARX_LSU1,Larx executed on LSU1
##0C77
Larx executed on LSU1
#46,u,g,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses
##0C12
LSU0 L1 D cache load misses
#47,u,g,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses
##0C16
LSU1 L1 D cache load misses
#48,u,g,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references
##0C10
LSU0 L1 D cache load references
#49,u,g,PM_LD_REF_L1_LSU1,LSU1 L1 D cache load references
##0C14
LSU1 L1 D cache load references
#50,u,g,PM_LSU0_BUSY,LSU0 busy
##0C33
LSU0 busy
#51,u,g,PM_LSU1_BUSY,LSU1 busy
##0C37
LSU1 busy
#52,u,g,PM_LSU_LMQ_S0_ALLOC,LMQ slot 0 allocated
##0935
LMQ slot 0 allocated
#53,u,g,PM_LSU_LMQ_S0_VALID,LMQ slot 0 valid
##0931
LMQ slot 0 valid
#54,u,g,PM_LSU_LRQ_FULL_CYC,Cycles LRQ full
##0112,0612
Cycles LRQ full
#55,u,g,PM_LSU_SRQ_FULL_CYC,Cycles SRQ full
##0113,0613
Cycles SRQ full
#56,u,g,PM_LSU_SRQ_SYNC_CYC,SRQ sync duration
##0932
SRQ sync duration
#57,u,g,PM_MRK_L1_RELOAD_VALID,Marked L1 reload data source valid
##0C74
Marked L1 reload data source valid
#58,u,g,PM_MRK_LSU0_FLUSH_LRQ,LSU0 marked LRQ flushes
##0912
LSU0 marked LRQ flushes
#59,u,g,PM_MRK_LSU0_FLUSH_SRQ,LSU0 marked SRQ flushes
##0913
LSU0 marked SRQ flushes
#60,u,g,PM_MRK_LSU0_FLUSH_ULD,LSU0 marked unaligned load flushes
##0911
LSU0 marked unaligned load flushes
#61,u,g,PM_MRK_LSU0_FLUSH_UST,LSU0 marked unaligned store flushes
##0910
LSU0 marked unaligned store flushes
#62,u,g,PM_MRK_LSU0_INST_FIN,LSU0 finished a marked instruction
##0C31
LSU0 finished a marked instruction
#63,u,g,PM_MRK_LSU1_FLUSH_LRQ,LSU1 marked LRQ flushes
##0916
LSU1 marked LRQ flushes
#64,u,g,PM_MRK_LSU1_FLUSH_SRQ,LSU1 marked SRQ flushes
##0917
LSU1 marked SRQ flushes
#65,u,g,PM_MRK_LSU1_FLUSH_ULD,LSU1 marked unaligned load flushes
##0915
LSU1 marked unaligned load flushes
#66,u,g,PM_MRK_LSU1_FLUSH_UST,LSU1 marked unaligned store flushes
##0914
LSU1 marked unaligned store flushes
#67,u,g,PM_MRK_LSU1_INST_FIN,LSU1 finished a marked instruction
##0C32
LSU1 finished a marked instruction
#68,u,g,PM_MRK_LSU_SRQ_INST_VALID,Marked instruction valid in SRQ
##0933
Marked instruction valid in SRQ
#69,u,g,PM_STCX_PASS,Stcx passes
##0C75
Stcx passes
#70,u,g,PM_ST_MISS_L1,L1 D cache store misses
##0C13
L1 D cache store misses
#71,u,g,PM_ST_REF_L1_LSU0,LSU0 L1 D cache store references
##0C11
LSU0 L1 D cache store references
#72,u,g,PM_ST_REF_L1_LSU1,LSU1 L1 D cache store references
##0C15
LSU1 L1 D cache store references
#73,u,g,PM_CYC,Processor cycles
##800F
Processor cycles
#74,u,g,PM_DATA_FROM_L2,Data loaded from L2
##8C66
Data loaded from L2
#75,u,g,PM_FPU_FIN,FPU produced a result
##8010
FPU produced a result
#76,u,g,PM_FXU1_BUSY_FXU0_IDLE,FXU1 busy FXU0 idle
##8002
FXU1 busy FXU0 idle
#77,u,g,PM_INST_CMPL,Instructions completed
##8001
Instructions completed
#78,u,g,PM_INST_FROM_L35,Instructions fetched from L3.5
##8227
Instructions fetched from L3.5
#79,u,g,PM_LARX,Larx executed
##8C70
Larx executed
#80,u,g,PM_LSU_BUSY,LSU busy
##8C30
LSU busy
#81,u,g,PM_LSU_SRQ_EMPTY_CYC,Cycles SRQ empty
##8003
Cycles SRQ empty
#82,u,g,PM_MRK_CRU_FIN,Marked instruction CRU processing finished
##8005
Marked instruction CRU processing finished
#83,u,g,PM_MRK_DATA_FROM_L2,Marked data loaded from L2
##8C76
Marked data loaded from L2
#84,u,g,PM_MRK_GRP_CMPL,Marked group completed
##8004
Marked group completed
#85,u,g,PM_MRK_LSU_FLUSH_SRQ,Marked SRQ flushes
##8910
Marked SRQ flushes
$$$$

{ counter 5 }
#0,u,g,PM_BIQ_IDU_FULL_CYC,Cycles BIQ or IDU full
##0224,0824
Cycles BIQ or IDU full
#1,u,g,PM_BRQ_FULL_CYC,Cycles branch queue full
##0105,0605
Cycles branch queue full
#2,u,g,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full
##0104,0604
Cycles CR logical operation mapper full
#3,u,g,PM_DC_PREF_L2_CLONE_L3,L2 prefetch cloned with L3
##0C27
L2 prefetch cloned with L3
#4,u,g,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated
##0907
D cache new prefetch stream allocated
#5,u,g,PM_DSLB_MISS,Data SLB misses
##0905
Data SLB misses
#6,u,g,PM_DTLB_MISS,Data TLB misses
##0904
Data TLB misses
#7,u,g,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full
##0101,0601
Cycles FPR mapper full
#8,u,g,PM_FPU0_ALL,FPU0 executed add, mult, sub, cmp or sel instruction
##0003
FPU0 executed add, mult, sub, cmp or sel instruction
#9,u,g,PM_FPU0_DENORM,FPU0 received denormalized data
##0020
FPU0 received denormalized data
#10,u,g,PM_FPU0_FDIV,FPU0 executed FDIV instruction
##0000
FPU0 executed FDIV instruction
#11,u,g,PM_FPU0_FMA,FPU0 executed multiply-add instruction
##0001
FPU0 executed multiply-add instruction
#12,u,g,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction
##0002
FPU0 executed FSQRT instruction
#13,u,g,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full
##0103,0603
Cycles FPU0 issue queue full
#14,u,g,PM_FPU0_SINGLE,FPU0 executed single precision instruction
##0023
FPU0 executed single precision instruction
#15,u,g,PM_FPU0_STALL3,FPU0 stalled in pipe3
##0021
FPU0 stalled in pipe3
#16,u,g,PM_FPU0_STF,FPU0 executed store instruction
##0022
FPU0 executed store instruction
#17,u,g,PM_FPU1_ALL,FPU1 executed add, mult, sub, cmp or sel instruction
##0007
FPU1 executed add, mult, sub, cmp or sel instruction
#18,u,g,PM_FPU1_DENORM,FPU1 received denormalized data
##0024
FPU1 received denormalized data
#19,u,g,PM_FPU1_FDIV,FPU1 executed FDIV instruction
##0004
FPU1 executed FDIV instruction
#20,u,g,PM_FPU1_FMA,FPU1 executed multiply-add instruction
##0005
FPU1 executed multiply-add instruction
#21,u,g,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction
##0006
FPU1 executed FSQRT instruction
#22,u,g,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full
##0107,0607
Cycles FPU1 issue queue full
#23,u,g,PM_FPU1_SINGLE,FPU1 executed single precision instruction
##0027
FPU1 executed single precision instruction
#24,u,g,PM_FPU1_STALL3,FPU1 stalled in pipe3
##0025
FPU1 stalled in pipe3
#25,u,g,PM_FPU1_STF,FPU1 executed store instruction
##0026
FPU1 executed store instruction
#26,u,g,PM_GCT_FULL_CYC,Cycles GCT full
##0100,0600
Cycles GCT full
#27,u,g,PM_GRP_DISP_REJECT,Group dispatch rejected
##0124,0624
Group dispatch rejected
#28,u,g,PM_GRP_DISP_VALID,Group dispatch valid
##0123,0623
Group dispatch valid
#29,u,g,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch buffer
##0225,0825
Instruction prefetched installed in prefetch buffer
#30,u,g,PM_IC_PREF_REQ,Instruction prefetch requests
##0226,0826
Instruction prefetch requests
#31,u,g,PM_IERAT_XLATE_WR,Translation written to ierat
##0227,0827
Translation written to ierat
#32,u,g,PM_INST_DISP,Instructions dispatched
##0121,0621
Instructions dispatched
#33,u,g,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched
##0223,0823
Cycles at least 1 instruction fetched
#34,u,g,PM_ISLB_MISS,Instruction SLB misses
##0901
Instruction SLB misses
#35,u,g,PM_ITLB_MISS,Instruction TLB misses
##0900
Instruction TLB misses
#36,u,g,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid
##0C64
L1 reload data source valid
#37,u,g,PM_L2SA_MOD_INV,L2 slice A transition from modified to invalid
##4007
L2 slice A transition from modified to invalid
#38,u,g,PM_L2SA_MOD_TAG,L2 slice A transition from modified to tagged
##4006
L2 slice A transition from modified to tagged
#39,u,g,PM_L2SA_SHR_INV,L2 slice A transition from shared to invalid
##4005
L2 slice A transition from shared to invalid
#40,u,g,PM_L2SA_SHR_MOD,L2 slice A transition from shared to modified
##4004
L2 slice A transition from shared to modified
#41,u,g,PM_L2SB_MOD_INV,L2 slice B transition from modified to invalid
##4023
L2 slice B transition from modified to invalid
#42,u,g,PM_L2SB_MOD_TAG,L2 slice B transition from modified to tagged
##4022
L2 slice B transition from modified to tagged
#43,u,g,PM_L2SB_SHR_INV,L2 slice B transition from shared to invalid
##4021
L2 slice B transition from shared to invalid
#44,u,g,PM_L2SB_SHR_MOD,L2 slice B transition from shared to modified
##4020
L2 slice B transition from shared to modified
#45,u,g,PM_L2SC_MOD_INV,L2 slice C transition from modified to invalid
##4027
L2 slice C transition from modified to invalid
#46,u,g,PM_L2SC_MOD_TAG,L2 slice C transition from modified to tagged
##4026
L2 slice C transition from modified to tagged
#47,u,g,PM_L2SC_SHR_INV,L2 slice C transition from shared to invalid
##4025
L2 slice C transition from shared to invalid
#48,u,g,PM_L2SC_SHR_MOD,L2 slice C transition from shared to modified
##4024
L2 slice C transition from shared to modified
#49,u,g,PM_L3B0_DIR_MIS,L3 bank 0 directory misses
##4001
L3 bank 0 directory misses
#50,u,g,PM_L3B0_DIR_REF,L3 bank 0 directory references
##4000
L3 bank 0 directory references
#51,u,g,PM_L3B1_DIR_MIS,L3 bank 1 directory misses
##4003
L3 bank 1 directory misses
#52,u,g,PM_L3B1_DIR_REF,L3 bank 1 directory references
##4002
L3 bank 1 directory references
#53,u,g,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full
##0106,0606
Cycles LR/CTR mapper full
#54,u,g,PM_LSU0_DERAT_MISS,LSU0 DERAT misses
##0902
LSU0 DERAT misses
#55,u,g,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes
##0C02
LSU0 LRQ flushes
#56,u,g,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes
##0C03
LSU0 SRQ flushes
#57,u,g,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes
##0C00
LSU0 unaligned load flushes
#58,u,g,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes
##0C01
LSU0 unaligned store flushes
#59,u,g,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded
##0C20
LSU0 SRQ store forwarded
#60,u,g,PM_LSU1_DERAT_MISS,LSU1 DERAT misses
##0906
LSU1 DERAT misses
#61,u,g,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes
##0C06
LSU1 LRQ flushes
#62,u,g,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes
##0C07
LSU1 SRQ flushes
#63,u,g,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes
##0C04
LSU1 unaligned load flushes
#64,u,g,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes
##0C05
LSU1 unaligned store flushes
#65,u,g,PM_LSU1_SRQ_STFWD,LSU0 SRQ store forwarded
##0C24
LSU0 SRQ store forwarded
#66,u,g,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full
##0927
Cycles LMQ full
#67,u,g,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges
##0926
LMQ LHR merges
#68,u,g,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated
##0C26
LRQ slot 0 allocated
#69,u,g,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid
##0C22
LRQ slot 0 valid
#70,u,g,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated
##0C25
SRQ slot 0 allocated
#71,u,g,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid
##0C21
SRQ slot 0 valid
#72,u,g,PM_MRK_IMR_RELOAD,Marked IMR reloaded
##0922
Marked IMR reloaded
#73,u,g,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses
##0920
LSU0 L1 D cache load misses
#74,u,g,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses
##0924
LSU1 L1 D cache load misses
#75,u,g,PM_MRK_STCX_FAIL,Marked STCX failed
##0925
Marked STCX failed
#76,u,g,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses
##0923
Marked L1 D cache store misses
#77,u,g,PM_SNOOP_TLBIE,Snoop TLBIE
##0903
Snoop TLBIE
#78,u,g,PM_STCX_FAIL,STCX failed
##0921
STCX failed
#79,u,g,PM_ST_MISS_L1,L1 D cache store misses
##0C23
L1 D cache store misses
#80,u,g,PM_XER_MAP_FULL_CYC,Cycles XER mapper full
##0102,0602
Cycles XER mapper full
#81,u,g,PM_1PLUS_PPC_CMPL,One or more PPC instruction completed
##8003
One or more PPC instruction completed
#82,u,g,PM_CYC,Processor cycles
##800F
Processor cycles
#83,u,g,PM_DATA_FROM_L25_SHR,Data loaded from L2.5 shared
##8C66
Data loaded from L2.5 shared
#84,u,g,PM_FPU_ALL,FPU executed add, mult, sub, cmp or sel instruction
##8000
FPU executed add, mult, sub, cmp or sel instruction
#85,u,g,PM_FPU_FULL_CYC,Cycles FPU issue queue full
##8100
Cycles FPU issue queue full
#86,u,g,PM_FPU_FULL_CYC,Cycles FPU issue queue full
##8600
Cycles FPU issue queue full
#87,u,g,PM_FPU_SINGLE,FPU executed single precision instruction
##8020
FPU executed single precision instruction
#88,u,g,PM_FXU_IDLE,FXU idle
##8002
FXU idle
#89,u,g,PM_GRP_DISP_SUCCESS,Group dispatch success
##8001
Group dispatch success
#90,u,g,PM_GRP_MRK,Group marked in IDU
##8004
Group marked in IDU
#91,u,g,PM_INST_FROM_L3,Instruction fetched from L3
##8227
Instruction fetched from L3
#92,u,g,PM_LSU_FLUSH_SRQ,SRQ flushes
##8C00
SRQ flushes
#93,u,g,PM_MRK_DATA_FROM_L25_SHR,Marked data loaded from L2.5 shared
##8C76
Marked data loaded from L2.5 shared
#94,u,g,PM_MRK_GRP_TIMEO,Marked group completion timeout
##8005
Marked group completion timeout
$$$$

{ counter 6 }
#0,u,g,PM_BIQ_IDU_FULL_CYC,Cycles BIQ or IDU full
##0224,0824
Cycles BIQ or IDU full
#1,u,g,PM_BRQ_FULL_CYC,Cycles branch queue full
##0105,0605
Cycles branch queue full
#2,u,g,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full
##0104,0604
Cycles CR logical operation mapper full
#3,u,g,PM_DC_PREF_L2_CLONE_L3,L2 prefetch cloned with L3
##0C27
L2 prefetch cloned with L3
#4,u,g,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated
##0907
D cache new prefetch stream allocated
#5,u,g,PM_DSLB_MISS,Data SLB misses
##0905
Data SLB misses
#6,u,g,PM_DTLB_MISS,Data TLB misses
##0904
Data TLB misses
#7,u,g,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full
##0101,0601
Cycles FPR mapper full
#8,u,g,PM_FPU0_ALL,FPU0 executed add, mult, sub, cmp or sel instruction
##0003
FPU0 executed add, mult, sub, cmp or sel instruction
#9,u,g,PM_FPU0_DENORM,FPU0 received denormalized data
##0020
FPU0 received denormalized data
#10,u,g,PM_FPU0_FDIV,FPU0 executed FDIV instruction
##0000
FPU0 executed FDIV instruction
#11,u,g,PM_FPU0_FMA,FPU0 executed multiply-add instruction
##0001
FPU0 executed multiply-add instruction
#12,u,g,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction
##0002
FPU0 executed FSQRT instruction
#13,u,g,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full
##0103,0603
Cycles FPU0 issue queue full
#14,u,g,PM_FPU0_SINGLE,FPU0 executed single precision instruction
##0023
FPU0 executed single precision instruction
#15,u,g,PM_FPU0_STALL3,FPU0 stalled in pipe3
##0021
FPU0 stalled in pipe3
#16,u,g,PM_FPU0_STF,FPU0 executed store instruction
##0022
FPU0 executed store instruction
#17,u,g,PM_FPU1_ALL,FPU1 executed add, mult, sub, cmp or sel instruction
##0007
FPU1 executed add, mult, sub, cmp or sel instruction
#18,u,g,PM_FPU1_DENORM,FPU1 received denormalized data
##0024
FPU1 received denormalized data
#19,u,g,PM_FPU1_FDIV,FPU1 executed FDIV instruction
##0004
FPU1 executed FDIV instruction
#20,u,g,PM_FPU1_FMA,FPU1 executed multiply-add instruction
##0005
FPU1 executed multiply-add instruction
#21,u,g,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction
##0006
FPU1 executed FSQRT instruction
#22,u,g,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full
##0107,0607
Cycles FPU1 issue queue full
#23,u,g,PM_FPU1_SINGLE,FPU1 executed single precision instruction
##0027
FPU1 executed single precision instruction
#24,u,g,PM_FPU1_STALL3,FPU1 stalled in pipe3
##0025
FPU1 stalled in pipe3
#25,u,g,PM_FPU1_STF,FPU1 executed store instruction
##0026
FPU1 executed store instruction
#26,u,g,PM_GCT_FULL_CYC,Cycles GCT full
##0100,0600
Cycles GCT full
#27,u,g,PM_GRP_DISP_REJECT,Group dispatch rejected
##0124,0624
Group dispatch rejected
#28,u,g,PM_GRP_DISP_VALID,Group dispatch valid
##0123,0623
Group dispatch valid
#29,u,g,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch buffer
##0225,0825
Instruction prefetched installed in prefetch buffer
#30,u,g,PM_IC_PREF_REQ,Instruction prefetch requests
##0226,0826
Instruction prefetch requests
#31,u,g,PM_IERAT_XLATE_WR,Translation written to ierat
##0227,0827
Translation written to ierat
#32,u,g,PM_INST_DISP,Instructions dispatched
##0121,0621
Instructions dispatched
#33,u,g,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched
##0223,0823
Cycles at least 1 instruction fetched
#34,u,g,PM_ISLB_MISS,Instruction SLB misses
##0901
Instruction SLB misses
#35,u,g,PM_ITLB_MISS,Instruction TLB misses
##0900
Instruction TLB misses
#36,u,g,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid
##0C64
L1 reload data source valid
#37,u,g,PM_L2SA_MOD_INV,L2 slice A transition from modified to invalid
##4007
L2 slice A transition from modified to invalid
#38,u,g,PM_L2SA_MOD_TAG,L2 slice A transition from modified to tagged
##4006
L2 slice A transition from modified to tagged
#39,u,g,PM_L2SA_SHR_INV,L2 slice A transition from shared to invalid
##4005
L2 slice A transition from shared to invalid
#40,u,g,PM_L2SA_SHR_MOD,L2 slice A transition from shared to modified
##4004
L2 slice A transition from shared to modified
#41,u,g,PM_L2SB_MOD_INV,L2 slice B transition from modified to invalid
##4023
L2 slice B transition from modified to invalid
#42,u,g,PM_L2SB_MOD_TAG,L2 slice B transition from modified to tagged
##4022
L2 slice B transition from modified to tagged
#43,u,g,PM_L2SB_SHR_INV,L2 slice B transition from shared to invalid
##4021
L2 slice B transition from shared to invalid
#44,u,g,PM_L2SB_SHR_MOD,L2 slice B transition from shared to modified
##4020
L2 slice B transition from shared to modified
#45,u,g,PM_L2SC_MOD_INV,L2 slice C transition from modified to invalid
##4027
L2 slice C transition from modified to invalid
#46,u,g,PM_L2SC_MOD_TAG,L2 slice C transition from modified to tagged
##4026
L2 slice C transition from modified to tagged
#47,u,g,PM_L2SC_SHR_INV,L2 slice C transition from shared to invalid
##4025
L2 slice C transition from shared to invalid
#48,u,g,PM_L2SC_SHR_MOD,L2 slice C transition from shared to modified
##4024
L2 slice C transition from shared to modified
#49,u,g,PM_L3B0_DIR_MIS,L3 bank 0 directory misses
##4001
L3 bank 0 directory misses
#50,u,g,PM_L3B0_DIR_REF,L3 bank 0 directory references
##4000
L3 bank 0 directory references
#51,u,g,PM_L3B1_DIR_MIS,L3 bank 1 directory misses
##4003
L3 bank 1 directory misses
#52,u,g,PM_L3B1_DIR_REF,L3 bank 1 directory references
##4002
L3 bank 1 directory references
#53,u,g,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full
##0106,0606
Cycles LR/CTR mapper full
#54,u,g,PM_LSU0_DERAT_MISS,LSU0 DERAT misses
##0902
LSU0 DERAT misses
#55,u,g,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes
##0C02
LSU0 LRQ flushes
#56,u,g,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes
##0C03
LSU0 SRQ flushes
#57,u,g,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes
##0C00
LSU0 unaligned load flushes
#58,u,g,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes
##0C01
LSU0 unaligned store flushes
#59,u,g,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded
##0C20
LSU0 SRQ store forwarded
#60,u,g,PM_LSU1_DERAT_MISS,LSU1 DERAT misses
##0906
LSU1 DERAT misses
#61,u,g,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes
##0C06
LSU1 LRQ flushes
#62,u,g,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes
##0C07
LSU1 SRQ flushes
#63,u,g,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes
##0C04
LSU1 unaligned load flushes
#64,u,g,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes
##0C05
LSU1 unaligned store flushes
#65,u,g,PM_LSU1_SRQ_STFWD,LSU0 SRQ store forwarded
##0C24
LSU0 SRQ store forwarded
#66,u,g,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full
##0927
Cycles LMQ full
#67,u,g,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges
##0926
LMQ LHR merges
#68,u,g,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated
##0C26
LRQ slot 0 allocated
#69,u,g,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid
##0C22
LRQ slot 0 valid
#70,u,g,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated
##0C25
SRQ slot 0 allocated
#71,u,g,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid
##0C21
SRQ slot 0 valid
#72,u,g,PM_MRK_IMR_RELOAD,Marked IMR reloaded
##0922
Marked IMR reloaded
#73,u,g,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses
##0920
LSU0 L1 D cache load misses
#74,u,g,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses
##0924
LSU1 L1 D cache load misses
#75,u,g,PM_MRK_STCX_FAIL,Marked STCX failed
##0925
Marked STCX failed
#76,u,g,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses
##0923
Marked L1 D cache store misses
#77,u,g,PM_SNOOP_TLBIE,Snoop TLBIE
##0903
Snoop TLBIE
#78,u,g,PM_STCX_FAIL,STCX failed
##0921
STCX failed
#79,u,g,PM_ST_MISS_L1,L1 D cache store misses
##0C23
L1 D cache store misses
#80,u,g,PM_XER_MAP_FULL_CYC,Cycles XER mapper full
##0102,0602
Cycles XER mapper full
#81,u,g,PM_CYC,Processor cycles
##800F
Processor cycles
#82,u,g,PM_DATA_FROM_L275_SHR,Data loaded from L2.75 shared
##8C66
Data loaded from L2.75 shared
#83,u,g,PM_FPU_FSQRT,FPU executed FSQRT instruction
##8000
FPU executed FSQRT instruction
#84,u,g,PM_FPU_STF,FPU executed store instruction
##8020
FPU executed store instruction
#85,u,g,PM_FXU_BUSY,FXU busy
##8002
FXU busy
#86,u,g,PM_INST_CMPL,Instructions completed
##8001
Instructions completed
#87,u,g,PM_INST_FROM_L1,Instruction fetched from L1
##8227
Instruction fetched from L1
#88,u,g,PM_LSU_DERAT_MISS,DERAT misses
##8900
DERAT misses
#89,u,g,PM_LSU_FLUSH_LRQ,LRQ flushes
##8C00
LRQ flushes
#90,u,g,PM_MRK_DATA_FROM_L275_SHR,Marked data loaded from L2.75 shared
##8C76
Marked data loaded from L2.75 shared
#91,u,g,PM_MRK_FXU_FIN,Marked instruction FXU processing finished
##8004
Marked instruction FXU processing finished
#92,u,g,PM_MRK_GRP_ISSUED,Marked group issued
##8005
Marked group issued
#93,u,g,PM_MRK_ST_GPS,Marked store sent to GPS
##8003
Marked store sent to GPS
$$$$

{ counter 7 }
#0,u,g,PM_1INST_CLB_CYC,Cycles 1 instruction in CLB
##0450
Cycles 1 instruction in CLB
#1,u,g,PM_2INST_CLB_CYC,Cycles 2 instructions in CLB
##0451
Cycles 2 instructions in CLB
#2,u,g,PM_3INST_CLB_CYC,Cycles 3 instructions in CLB
##0452
Cycles 3 instructions in CLB
#3,u,g,PM_4INST_CLB_CYC,Cycles 4 instructions in CLB
##0453
Cycles 4 instructions in CLB
#4,u,g,PM_5INST_CLB_CYC,Cycles 5 instructions in CLB
##0454
Cycles 5 instructions in CLB
#5,u,g,PM_6INST_CLB_CYC,Cycles 6 instructions in CLB
##0455
Cycles 6 instructions in CLB
#6,u,g,PM_7INST_CLB_CYC,Cycles 7 instructions in CLB
##0456
Cycles 7 instructions in CLB
#7,u,g,PM_8INST_CLB_CYC,Cycles 8 instructions in CLB
##0457
Cycles 8 instructions in CLB
#8,u,g,PM_BR_ISSUED,Branches issued
##0230,0830
Branches issued
#9,u,g,PM_BR_MPRED_CR,Branch mispredictions due CR bit setting
##0231,0831
Branch mispredictions due CR bit setting
#10,u,g,PM_BR_MPRED_TA,Branch mispredictions due to target address
##0232,0832
Branch mispredictions due to target address
#11,u,g,PM_CRQ_FULL_CYC,Cycles CR issue queue full
##0111,0611
Cycles CR issue queue full
#12,u,g,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks
##0936
Cycles doing data tablewalks
#13,u,g,PM_DC_INV_L2,L1 D cache entries invalidated from L2
##0C17
L1 D cache entries invalidated from L2
#14,u,g,PM_DC_PREF_OUT_STREAMS,Out of prefetch streams
##0C36
Out of prefetch streams
#15,u,g,PM_EE_OFF,Cycles MSR(EE) bit off
##0133,0633
Cycles MSR(EE) bit off
#16,u,g,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending
##0137,0637
Cycles MSR(EE) bit off and external interrupt pending
#17,u,g,PM_FAB_CMD_ISSUED,Fabric command issued
##4016
Fabric command issued
#18,u,g,PM_FAB_CMD_RETRIED,Fabric command retried
##4017
Fabric command retried
#19,u,g,PM_LSU0_LDF,LSU0 executed Floating Point load instruction
##0930
LSU0 executed Floating Point load instruction
#20,u,g,PM_LSU1_LDF,LSU1 executed Floating Point load instruction
##0934
LSU1 executed Floating Point load instruction
#21,u,g,PM_FPU0_FEST,FPU0 executed FEST instruction
##0012
FPU0 executed FEST instruction
#22,u,g,PM_FPU0_FIN,FPU0 produced a result
##0013
FPU0 produced a result
#23,u,g,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions
##0010
FPU0 executed FMOV or FEST instructions
#24,u,g,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction
##0030
FPU0 executed FPSCR instruction
#25,u,g,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions
##0011
FPU0 executed FRSP or FCONV instructions
#26,u,g,PM_FPU1_FEST,FPU1 executed FEST instruction
##0016
FPU1 executed FEST instruction
#27,u,g,PM_FPU1_FIN,FPU1 produced a result
##0017
FPU1 produced a result
#28,u,g,PM_FPU1_FMOV_FEST,FPU0 executing FMOV or FEST instructions
##0014
FPU0 executing FMOV or FEST instructions
#29,u,g,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions
##0015
FPU1 executed FRSP or FCONV instructions
#30,u,g,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full
##0110,0114,0610,0614
Cycles FXU0/LS0 queue full
#31,u,g,PM_FXU0_FIN,FXU0 produced a result
##0132,0632
FXU0 produced a result
#32,u,g,PM_FXU1_FIN,FXU1 produced a result
##0136,0636
FXU1 produced a result
#33,u,g,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full
##0135,0635
Cycles GPR mapper full
#34,u,g,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard
##0131,0631
Cycles group dispatch blocked by scoreboard
#35,u,g,PM_L1_PREF,L1 cache data prefetches
##0C35
L1 cache data prefetches
#36,u,g,PM_L1_WRITE_CYC,Cycles writing to instruction L1
##0233,0833
Cycles writing to instruction L1
#37,u,g,PM_L2SA_ST_HIT,L2 slice A store hits
##4011
L2 slice A store hits
#38,u,g,PM_L2SA_ST_REQ,L2 slice A store requests
##4010
L2 slice A store requests
#39,u,g,PM_L2SB_ST_HIT,L2 slice B store hits
##4013
L2 slice B store hits
#40,u,g,PM_L2SB_ST_REQ,L2 slice B store requests
##4012
L2 slice B store requests
#41,u,g,PM_L2SC_ST_HIT,L2 slice C store hits
##4015
L2 slice C store hits
#42,u,g,PM_L2SC_ST_REQ,L2 slice C store requests
##4014
L2 slice C store requests
#43,u,g,PM_L2_PREF,L2 cache prefetches
##0C34
L2 cache prefetches
#44,u,g,PM_LARX_LSU0,Larx executed on LSU0
##0C73
Larx executed on LSU0
#45,u,g,PM_LARX_LSU1,Larx executed on LSU1
##0C77
Larx executed on LSU1
#46,u,g,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses
##0C12
LSU0 L1 D cache load misses
#47,u,g,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses
##0C16
LSU1 L1 D cache load misses
#48,u,g,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references
##0C10
LSU0 L1 D cache load references
#49,u,g,PM_LD_REF_L1_LSU1,LSU1 L1 D cache load references
##0C14
LSU1 L1 D cache load references
#50,u,g,PM_LSU0_BUSY,LSU0 busy
##0C33
LSU0 busy
#51,u,g,PM_LSU1_BUSY,LSU1 busy
##0C37
LSU1 busy
#52,u,g,PM_LSU_LMQ_S0_ALLOC,LMQ slot 0 allocated
##0935
LMQ slot 0 allocated
#53,u,g,PM_LSU_LMQ_S0_VALID,LMQ slot 0 valid
##0931
LMQ slot 0 valid
#54,u,g,PM_LSU_LRQ_FULL_CYC,Cycles LRQ full
##0112,0612
Cycles LRQ full
#55,u,g,PM_LSU_SRQ_FULL_CYC,Cycles SRQ full
##0113,0613
Cycles SRQ full
#56,u,g,PM_LSU_SRQ_SYNC_CYC,SRQ sync duration
##0932
SRQ sync duration
#57,u,g,PM_MRK_L1_RELOAD_VALID,Marked L1 reload data source valid
##0C74
Marked L1 reload data source valid
#58,u,g,PM_MRK_LSU0_FLUSH_LRQ,LSU0 marked LRQ flushes
##0912
LSU0 marked LRQ flushes
#59,u,g,PM_MRK_LSU0_FLUSH_SRQ,LSU0 marked SRQ flushes
##0913
LSU0 marked SRQ flushes
#60,u,g,PM_MRK_LSU0_FLUSH_ULD,LSU0 marked unaligned load flushes
##0911
LSU0 marked unaligned load flushes
#61,u,g,PM_MRK_LSU0_FLUSH_UST,LSU0 marked unaligned store flushes
##0910
LSU0 marked unaligned store flushes
#62,u,g,PM_MRK_LSU0_INST_FIN,LSU0 finished a marked instruction
##0C31
LSU0 finished a marked instruction
#63,u,g,PM_MRK_LSU1_FLUSH_LRQ,LSU1 marked LRQ flushes
##0916
LSU1 marked LRQ flushes
#64,u,g,PM_MRK_LSU1_FLUSH_SRQ,LSU1 marked SRQ flushes
##0917
LSU1 marked SRQ flushes
#65,u,g,PM_MRK_LSU1_FLUSH_ULD,LSU1 marked unaligned load flushes
##0915
LSU1 marked unaligned load flushes
#66,u,g,PM_MRK_LSU1_FLUSH_UST,LSU1 marked unaligned store flushes
##0914
LSU1 marked unaligned store flushes
#67,u,g,PM_MRK_LSU1_INST_FIN,LSU1 finished a marked instruction
##0C32
LSU1 finished a marked instruction
#68,u,g,PM_MRK_LSU_SRQ_INST_VALID,Marked instruction valid in SRQ
##0933
Marked instruction valid in SRQ
#69,u,g,PM_STCX_PASS,Stcx passes
##0C75
Stcx passes
#70,u,g,PM_ST_MISS_L1,L1 D cache store misses
##0C13
L1 D cache store misses
#71,u,g,PM_ST_REF_L1_LSU0,LSU0 L1 D cache store references
##0C11
LSU0 L1 D cache store references
#72,u,g,PM_ST_REF_L1_LSU1,LSU1 L1 D cache store references
##0C15
LSU1 L1 D cache store references
#73,u,g,PM_CYC,Processor cycles
##800F
Processor cycles
#74,u,g,PM_DATA_FROM_L275_MOD,Data loaded from L2.75 modified
##8C66
Data loaded from L2.75 modified
#75,u,g,PM_FPU_FRSP_FCONV,FPU executed FRSP or FCONV instructions
##8010
FPU executed FRSP or FCONV instructions
#76,u,g,PM_FXU0_BUSY_FXU1_IDLE,FXU0 busy FXU1 idle
##8002
FXU0 busy FXU1 idle
#77,u,g,PM_GRP_CMPL,Group completed
##8003
Group completed
#78,u,g,PM_INST_CMPL,Instructions completed
##8001
Instructions completed
#79,u,g,PM_INST_FROM_PREF,Instructions fetched from prefetch
##8227
Instructions fetched from prefetch
#80,u,g,PM_MRK_DATA_FROM_L275_MOD,Marked data loaded from L2.75 modified
##8C76
Marked data loaded from L2.75 modified
#81,u,g,PM_MRK_FPU_FIN,Marked instruction FPU processing finished
##8004
Marked instruction FPU processing finished
#82,u,g,PM_MRK_INST_FIN,Marked instruction finished
##8005
Marked instruction finished
#83,u,g,PM_MRK_LSU_FLUSH_UST,Marked unaligned store flushes
##8910
Marked unaligned store flushes
#84,u,g,PM_ST_REF_L1,L1 D cache store references
##8C10
L1 D cache store references
$$$$

{ counter 8 }
#0,u,g,PM_1INST_CLB_CYC,Cycles 1 instruction in CLB
##0450
Cycles 1 instruction in CLB
#1,u,g,PM_2INST_CLB_CYC,Cycles 2 instructions in CLB
##0451
Cycles 2 instructions in CLB
#2,u,g,PM_3INST_CLB_CYC,Cycles 3 instructions in CLB
##0452
Cycles 3 instructions in CLB
#3,u,g,PM_4INST_CLB_CYC,Cycles 4 instructions in CLB
##0453
Cycles 4 instructions in CLB
#4,u,g,PM_5INST_CLB_CYC,Cycles 5 instructions in CLB
##0454
Cycles 5 instructions in CLB
#5,u,g,PM_6INST_CLB_CYC,Cycles 6 instructions in CLB
##0455
Cycles 6 instructions in CLB
#6,u,g,PM_7INST_CLB_CYC,Cycles 7 instructions in CLB
##0456
Cycles 7 instructions in CLB
#7,u,g,PM_8INST_CLB_CYC,Cycles 8 instructions in CLB
##0457
Cycles 8 instructions in CLB
#8,u,g,PM_BR_ISSUED,Branches issued
##0230,0830
Branches issued
#9,u,g,PM_BR_MPRED_CR,Branch mispredictions due CR bit setting
##0231,0831
Branch mispredictions due CR bit setting
#10,u,g,PM_BR_MPRED_TA,Branch mispredictions due to target address
##0232,0832
Branch mispredictions due to target address
#11,u,g,PM_CRQ_FULL_CYC,Cycles CR issue queue full
##0111,0611
Cycles CR issue queue full
#12,u,g,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks
##0936
Cycles doing data tablewalks
#13,u,g,PM_DC_INV_L2,L1 D cache entries invalidated from L2
##0C17
L1 D cache entries invalidated from L2
#14,u,g,PM_DC_PREF_OUT_STREAMS,Out of prefetch streams
##0C36
Out of prefetch streams
#15,u,g,PM_EE_OFF,Cycles MSR(EE) bit off
##0133,0633
Cycles MSR(EE) bit off
#16,u,g,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending
##0137,0637
Cycles MSR(EE) bit off and external interrupt pending
#17,u,g,PM_FAB_CMD_ISSUED,Fabric command issued
##4016
Fabric command issued
#18,u,g,PM_FAB_CMD_RETRIED,Fabric command retried
##4017
Fabric command retried
#19,u,g,PM_LSU0_LDF,LSU0 executed Floating Point load instruction
##0930
LSU0 executed Floating Point load instruction
#20,u,g,PM_LSU1_LDF,LSU1 executed Floating Point load instruction
##0934
LSU1 executed Floating Point load instruction
#21,u,g,PM_FPU0_FEST,FPU0 executed FEST instruction
##0012
FPU0 executed FEST instruction
#22,u,g,PM_FPU0_FIN,FPU0 produced a result
##0013
FPU0 produced a result
#23,u,g,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions
##0010
FPU0 executed FMOV or FEST instructions
#24,u,g,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction
##0030
FPU0 executed FPSCR instruction
#25,u,g,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions
##0011
FPU0 executed FRSP or FCONV instructions
#26,u,g,PM_FPU1_FEST,FPU1 executed FEST instruction
##0016
FPU1 executed FEST instruction
#27,u,g,PM_FPU1_FIN,FPU1 produced a result
##0017
FPU1 produced a result
#28,u,g,PM_FPU1_FMOV_FEST,FPU0 executing FMOV or FEST instructions
##0014
FPU0 executing FMOV or FEST instructions
#29,u,g,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions
##0015
FPU1 executed FRSP or FCONV instructions
#30,u,g,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full
##0110,0114,0610,0614
Cycles FXU0/LS0 queue full
#31,u,g,PM_FXU0_FIN,FXU0 produced a result
##0132,0632
FXU0 produced a result
#32,u,g,PM_FXU1_FIN,FXU1 produced a result
##0136,0636
FXU1 produced a result
#33,u,g,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full
##0135,0635
Cycles GPR mapper full
#34,u,g,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard
##0131,0631
Cycles group dispatch blocked by scoreboard
#35,u,g,PM_L1_PREF,L1 cache data prefetches
##0C35
L1 cache data prefetches
#36,u,g,PM_L1_WRITE_CYC,Cycles writing to instruction L1
##0233,0833
Cycles writing to instruction L1
#37,u,g,PM_L2SA_ST_HIT,L2 slice A store hits
##4011
L2 slice A store hits
#38,u,g,PM_L2SA_ST_REQ,L2 slice A store requests
##4010
L2 slice A store requests
#39,u,g,PM_L2SB_ST_HIT,L2 slice B store hits
##4013
L2 slice B store hits
#40,u,g,PM_L2SB_ST_REQ,L2 slice B store requests
##4012
L2 slice B store requests
#41,u,g,PM_L2SC_ST_HIT,L2 slice C store hits
##4015
L2 slice C store hits
#42,u,g,PM_L2SC_ST_REQ,L2 slice C store requests
##4014
L2 slice C store requests
#43,u,g,PM_L2_PREF,L2 cache prefetches
##0C34
L2 cache prefetches
#44,u,g,PM_LARX_LSU0,Larx executed on LSU0
##0C73
Larx executed on LSU0
#45,u,g,PM_LARX_LSU1,Larx executed on LSU1
##0C77
Larx executed on LSU1
#46,u,g,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses
##0C12
LSU0 L1 D cache load misses
#47,u,g,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses
##0C16
LSU1 L1 D cache load misses
#48,u,g,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references
##0C10
LSU0 L1 D cache load references
#49,u,g,PM_LD_REF_L1_LSU1,LSU1 L1 D cache load references
##0C14
LSU1 L1 D cache load references
#50,u,g,PM_LSU0_BUSY,LSU0 busy
##0C33
LSU0 busy
#51,u,g,PM_LSU1_BUSY,LSU1 busy
##0C37
LSU1 busy
#52,u,g,PM_LSU_LMQ_S0_ALLOC,LMQ slot 0 allocated
##0935
LMQ slot 0 allocated
#53,u,g,PM_LSU_LMQ_S0_VALID,LMQ slot 0 valid
##0931
LMQ slot 0 valid
#54,u,g,PM_LSU_LRQ_FULL_CYC,Cycles LRQ full
##0112,0612
Cycles LRQ full
#55,u,g,PM_LSU_SRQ_FULL_CYC,Cycles SRQ full
##0113,0613
Cycles SRQ full
#56,u,g,PM_LSU_SRQ_SYNC_CYC,SRQ sync duration
##0932
SRQ sync duration
#57,u,g,PM_MRK_L1_RELOAD_VALID,Marked L1 reload data source valid
##0C74
Marked L1 reload data source valid
#58,u,g,PM_MRK_LSU0_FLUSH_LRQ,LSU0 marked LRQ flushes
##0912
LSU0 marked LRQ flushes
#59,u,g,PM_MRK_LSU0_FLUSH_SRQ,LSU0 marked SRQ flushes
##0913
LSU0 marked SRQ flushes
#60,u,g,PM_MRK_LSU0_FLUSH_ULD,LSU0 marked unaligned load flushes
##0911
LSU0 marked unaligned load flushes
#61,u,g,PM_MRK_LSU0_FLUSH_UST,LSU0 marked unaligned store flushes
##0910
LSU0 marked unaligned store flushes
#62,u,g,PM_MRK_LSU0_INST_FIN,LSU0 finished a marked instruction
##0C31
LSU0 finished a marked instruction
#63,u,g,PM_MRK_LSU1_FLUSH_LRQ,LSU1 marked LRQ flushes
##0916
LSU1 marked LRQ flushes
#64,u,g,PM_MRK_LSU1_FLUSH_SRQ,LSU1 marked SRQ flushes
##0917
LSU1 marked SRQ flushes
#65,u,g,PM_MRK_LSU1_FLUSH_ULD,LSU1 marked unaligned load flushes
##0915
LSU1 marked unaligned load flushes
#66,u,g,PM_MRK_LSU1_FLUSH_UST,LSU1 marked unaligned store flushes
##0914
LSU1 marked unaligned store flushes
#67,u,g,PM_MRK_LSU1_INST_FIN,LSU1 finished a marked instruction
##0C32
LSU1 finished a marked instruction
#68,u,g,PM_MRK_LSU_SRQ_INST_VALID,Marked instruction valid in SRQ
##0933
Marked instruction valid in SRQ
#69,u,g,PM_STCX_PASS,Stcx passes
##0C75
Stcx passes
#70,u,g,PM_ST_MISS_L1,L1 D cache store misses
##0C13
L1 D cache store misses
#71,u,g,PM_ST_REF_L1_LSU0,LSU0 L1 D cache store references
##0C11
LSU0 L1 D cache store references
#72,u,g,PM_ST_REF_L1_LSU1,LSU1 L1 D cache store references
##0C15
LSU1 L1 D cache store references
#73,u,g,PM_0INST_FETCH,No instructions fetched
##8227
No instructions fetched
#74,u,g,PM_CYC,Processor cycles
##800F
Processor cycles
#75,u,g,PM_DATA_FROM_L25_MOD,Data loaded from L2.5 modified
##8C66
Data loaded from L2.5 modified
#76,u,g,PM_EXT_INT,External interrupts
##8002
External interrupts
#77,u,g,PM_FPU_FMOV_FEST,FPU executing FMOV or FEST instructions
##8010
FPU executing FMOV or FEST instructions
#78,u,g,PM_LSU_LDF,LSU executed Floating Point load instruction
##8930
LSU executed Floating Point load instruction
#79,u,g,PM_FXLS_FULL_CYC,Cycles FXLS queue is full
##8110
Cycles FXLS queue is full
#80,u,g,PM_GRP_DISP_REJECT,Group dispatch rejected
##8003
Group dispatch rejected
#81,u,g,PM_INST_CMPL,Instructions completed
##8001
Instructions completed
#82,u,g,PM_LD_REF_L1,L1 D cache load references
##8C10
L1 D cache load references
#83,u,g,PM_MRK_DATA_FROM_L25_MOD,Marked data loaded from L2.5 modified
##8C76
Marked data loaded from L2.5 modified
#84,u,g,PM_MRK_LSU_FIN,Marked instruction LSU processing finished
##8004
Marked instruction LSU processing finished
#85,u,g,PM_MRK_LSU_FLUSH_ULD,Marked unaligned load flushes
##8910
Marked unaligned load flushes
#86,u,g,PM_TB_BIT_TRANS,Time Base bit transition
##8005
Time Base bit transition