MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 471
BEGIN_KEYWORDS
INTERNATIONAL ACCESS MOSIS IC PROTOTYPING
END_KEYWORDS
DATE: october 1995
TITLE: International Access to MOSIS IC Prototyping



International Access to MOSIS IC Prototyping

(Contributed by Cesar Pina of MOSIS)

The MOSIS Service is a low-cost prototyping and small volume
production service for custom and semi-custom VLSI circuit
development. Available technologies include digital CMOS, mixed signal
(analog) CMOS, GaAs, and multi-chip (MCM) fabrication. Since its
start, the Service has processed in excess of 25,000 IC designs
through several different fabricators and technologies.  Currently,
fast-turnaround fabrication of integrated circuits is available
through a number of major commercial IC fabrication vendors such as
Hewlett-Packard, Orbit, Vitesse, and AMI.  This service is now
available to designers world-wide and special educational discounts
are available for all non-U.S. educational institutions.

The low project cost is achieved through cost sharing in each
fabrication run. Cost sharing results from the merging of the circuit
designs submitted by the different customers onto one phototooling
mask set, and the use of this mask set to fabricate the multiproject
wafers. When the fabrication run is completed and the wafers are
accepted by MOSIS, the wafers are sent to commercial assembly houses,
where the individual IC designs are separated and packaged. The
packaged parts (or bare die, depending on the customers' preference)
are then shipped to the customer. This approach results in significant
cost savings for prototype quantities.

Designers can submit layout design files via email or on magnetic
media in one of the commonly used geometrical description formats:
Calma GDSII, MEBES or CIF. Assembled devices are shipped to the
customers approximately eight weeks after the fab run closing date.

Wafer fabrication runs are scheduled on a regular basis for advanced
CMOS and GaAs technologies. For CMOS designs, several sets of layout
design rules are supported: MOSIS' public-domain scalable rules, a set
of DoD-developed scalable rules, and the fabricators' rules. These
design rules, as well as other design information, can be obtained
electronically as described in the next paragraph.

An extensive body of online information can be accessed over the
Internet via email, FTP or Mosaic. For email requests send an initial
message to mosis-help@isi.edu. For FTP access, first FTP to our host
FTP.MOSIS.EDU. Once connected, login as anonymous, supply your
net-address as password, then cd to pub/mosis. The file called
directory-tree.inf shows the contents of the entire file system. 
For Mosaic users, the same information can be accessed via 
MOSIS.  Questions about any of the
information can be addressed to mosis-help@isi.edu.

MOSIS now offers a layout design rule checking service.  The DRC
service supports MOSIS, DoD (i.e., CMOSN) and Vendor design rules for
CMOS runs and Vitesse HGaAs3 rules for GaAS.  Layout files must be
received 1 week prior to the run closing of their target run.
Projects intended for reticle runs (i.e., HGaAs3, CMOS34, CMOS26B) are
priced based on total project area: Please address comments or
questions to mosis-help@mosis.edu.
                                                                            
MOSIS now offers designers the opportunity to generate their designs
on MOSIS-supplied design kits that run with Viewlogic tools and submit
them as netlists.  The cost for each design iteration is $2,000.

For further information, contact:

Sam Reynolds
TEL: (310)-822-1511
FAX: (310)-823-5624 
sdreynolds@mosis.edu   

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