Design Capture HDL2Graphics: Documentation Visualization Animate Simulation Debugging (dynamic animation or visualization) Graphics2HDL: Most straightforward transcription of some ideas into the machine May improve productivity by reducing errors but may degrade productivity by taking longer to enter. Can copy old design in either case. Driving Design Flow GUI -- graphical entry presents only valid choices and can guide user. May improve productivity by reducing errors but may degrade productivity by taking longer to enter. CLI -- command lines (script) is generally faster and can use old script as a guide. Great for iterations. Altera_tools: Cheap, work only for Altera parts, skips pre-layout simulation due to historical PLD usage VHDL is a sub-set of the standard Generic tools: 1. VHDL --> Behavior Simulation 2. VHDL --> Synthesis (optimize and map into a library) 3. Netlist --> Functional Simulation (component timing only) 4. Netlist --> PAR (place and route with specific library) 5. Netlist' --> Post-layout Simulation (all timing) 6. Configure --> FPGA Part Can handle large designs by catching errors early. Can retarget to other FPGAs and even ASICs.