shft.vhd

LIBRARY ieee;
USE     ieee.std_logic_1164.all;

-- 8-bit Universal Bidirectional Shift register with parallel load and
-- Asynchronous reset.

ENTITY shft IS
  PORT (
    par_in  : IN     std_logic_vector(7 DOWNTO 0);
    ser_left: IN     std_logic;
    ser_rite: IN     std_logic;
    clk     : IN     std_logic;
    mode    : IN     std_logic_vector(1 DOWNTO 0);
    clear   : IN     std_logic;
    qout    : BUFFER std_logic_vector(7 DOWNTO 0)
  );
END shft;

ARCHITECTURE one OF shft IS
  SIGNAL enable: std_logic;
BEGIN
  enable <= '0' WHEN (mode = "00") else '1';

  PROCESS 
  BEGIN
    WAIT UNTIL (prising(clk) AND enable = '1') OR clear = '1';
    IF (clear = '1') THEN
      qout <= "00000000";
    ELSE
      CASE mode IS
        WHEN "01"   =>  
          qout <= ser_rite & qout(7 DOWNTO 1);   -- Shift Right
        WHEN "10"   =>                        
          qout <= qout(6 DOWNTO 0) & ser_left;   -- Shift Left
        WHEN "11"   =>  
          qout <= par_in;                        -- Parallel Load
        WHEN OTHERS => 
          null;
      END CASE;
    END IF;
  END PROCESS;

END one;