Checking out Encounter license ... Encounter_Digital_Impl_Sys_XL 9.1 license checkout succeeded. You can run 2 CPU jobs with the base license that is currently checked out. If required, use the setMultiCpuUsage command to enable multi-CPU processing. This Encounter release has been compiled with OA version 22.04-p061. ******************************************************************* * Copyright (c) Cadence Design Systems, Inc. 1996 - 2010. * * All rights reserved. * * * * * * * * This program contains confidential and trade secret information * * of Cadence Design Systems, Inc. and is protected by copyright * * law and international treaties. Any reproduction, use, * * distribution or disclosure of this program or any portion of it,* * or any attempt to obtain a human-readable version of this * * program, without the express, prior written consent of * * Cadence Design Systems, Inc., is strictly prohibited. * * * * Cadence Design Systems, Inc. * * 2655 Seely Avenue * * San Jose, CA 95134, USA * * * * * ******************************************************************* @(#)CDS: Encounter v09.12-s159_1 (64bit) 07/15/2010 13:17 (Linux 2.6) @(#)CDS: NanoRoute v09.12-s013 NR100629-2344/USR64-UB (database version 2.30, 102.1.1) {superthreading v1.15} @(#)CDS: CeltIC v09.12-s012_1 (64bit) 07/01/2010 05:52:50 (Linux 2.6.9-78.0.17.ELsmp) @(#)CDS: AAE 09.12-e022 (64bit) 07/15/2010 (Linux 2.6.9-89.0.19.ELsmp) @(#)CDS: CTE 09.12-s069_1 (64bit) Jul 15 2010 05:35:17 (Linux 2.6.9-89.0.19.ELsmp) @(#)CDS: CPE v09.12-s009 --- Starting "Encounter v09.12-s159_1" on Mon Oct 4 16:45:52 2010 (mem=60.0M) --- --- Running on ada8.eecs.utk.edu (x86_64 w/Linux 2.6.18-194.11.4.el5) --- This version was compiled on Thu Jul 15 13:17:23 PDT 2010. Set DBUPerIGU to 1000. Set net toggle Scale Factor to 1.00 Set Shrink Factor to 1.00000 Sourcing tcl/tk file "partb1.tcl" ... loadConfig ./encounter.conf Reading config file - ./encounter.conf **WARN: (ENCEXT-1085): Option 'rda_Input(ui_res_scale)' used in configuration file './encounter.conf' is obsolete. The name will be converted into new format automatically if design is saved and then restored. Alternatively, update the configuration file to use names 'rda_Input(ui_preRoute_res)' and/or 'rda_Input(ui_postRoute_res)' for resistance scale factors to be used at preRoute/postRoute stages of the design . The obsolete name works in this release. But to avoid this warning and to ensure compatibility with future releases, update this option name. Loading Lef file /sw/cadence/FreePDK45-1.3/osu_soc/lib/files/gscl45nm.lef... **WARN: (ENCLF-155): ViaRule only supports routing/cut layer, but poly layer found for viaRule 'M1_POLY', Set DBUPerIGU to M2 pitch 380. Initializing default via types and wire widths ... Power Planner/ViaGen version 8.1.46 promoted on 02/17/2009. viaInitial starts at Mon Oct 4 16:46:10 2010 viaInitial ends at Mon Oct 4 16:46:10 2010 Reading netlist ... Backslashed names will retain backslash and a trailing blank character. Reading verilog netlist 'circuit.v' *** Memory Usage v0.159.2.9 (Current mem = 325.461M, initial mem = 60.020M) *** *** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=325.5M) *** Set top cell to circuit. **WARN: (ENCSYC-2): Timing is not defined for cell INVX1. **WARN: (ENCSYC-2): Timing is not defined for cell FAX1. *** End library_loading (cpu=0.00min, mem=0.1M, fe_cpu=0.05min, fe_mem=325.6M) *** Starting recursive module instantiation check. No recursion found. Building hierarchical netlist for Cell circuit ... *** Netlist is unique. Set DBUPerIGU to techSite CoreSite width 760. ** info: there are 34 modules. ** info: there are 10 stdCell insts. *** Memory Usage v0.159.2.9 (Current mem = 326.098M, initial mem = 60.020M) *** *info: set bottom ioPad orient R0 Horizontal Layer M1 offset = 190 (guessed) Vertical Layer M2 offset = 190 (guessed) Suggestion: specify LAYER OFFSET in LEF file Reason: hard to extract LAYER OFFSET from standard cells Set Using Default Delay Limit as 1000. Set Default Net Delay as 1000 ps. Set Default Net Load as 0.5 pF. Set Input Pin Transition Delay as 120 ps. PreRoute Cap Scale Factor : 1.00 PreRoute Res Scale Factor : 1.00 PostRoute Cap Scale Factor : 1.00 PostRoute Res Scale Factor : 1.00 PostRoute XCap Scale Factor : 1.00 PreRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)] PreRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)] PostRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)] PostRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)] **WARN: (ENCOPT-3465): The buffer cells were automatically identified. The command setBufFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command. **WARN: (ENCOPT-3466): The inverter cells were automatically identified. The command setInvFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command. **WARN: (ENCOPT-3467): The delay cells were automatically identified. The command setDelayFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command. floorPlan -r 0.5 1.0 Original cellDensity(chipDen)=1.000, nrRow=1. Number of standard cell rows = 1. Horizontal Layer M1 offset = 190 (guessed) Vertical Layer M2 offset = 190 (guessed) Suggestion: specify LAYER OFFSET in LEF file Reason: hard to extract LAYER OFFSET from standard cells amoebaPlace **WARN: (ENCSP-9007): The command 'amoebaPlace' is obsolete. It has been replaced by 'placeDesign'. Extracting standard cell pins and blockage ...... Pin and blockage extraction finished Extracting macro/IO cell pins and blockage ...... Pin and blockage extraction finished *** Starting "NanoPlace(TM) placement v0.892.2.15 (mem=326.3M)" ... Options: ignoreScan ignoreSpare pinGuide gpeffort=medium **WARN: (ENCDB-2082): Scan chains were not defined, -ignoreScan option will be ignored. Please first define the scan chains before using this option. #std cell=10 #block=0 (0 floating + 0 preplaced) #ioInst=0 #net=17 #term=40 #term/net=2.35, #fixedIo=0, #floatIo=0, #fixedPin=0, #floatPin=8 stdCell: 10 single + 0 double + 0 multi Total standard cell length = 0.0179 (mm), area = 0.0000 (mm^2) Design contains fractional 20 cells. Average module density = 1.000. Density for the design = 1.000. = stdcell_area 47 (44 um^2) / alloc_area 47 (44 um^2). Pin Density = 0.851. = total # of pins 40 / total Instance area 47. Iteration 1: Total net bbox = 7.566e+01 (6.65e+01 9.12e+00) Est. stn bbox = 7.782e+01 (6.86e+01 9.23e+00) cpu = 0:00:00.0 real = 0:00:00.0 mem = 327.4M *** cost = 7.566e+01 (6.65e+01 9.12e+00) (cpu for global=0:00:00.0) real=0:00:00.0*** Design contains fractional 20 cells. Starting refinePlace ... **ERROR: (ENCSP-2002): Density too high (100.0%). Stopping detail placement. Total net length = 8.717e+01 (7.806e+01 9.120e+00) (ext = 3.630e+01) *** End of Placement (cpu=0:00:00.0, real=0:00:00.0, mem=327.4M) *** Design contains fractional 20 cells. default core: bins with density > 0.75 = 100 % ( 1 / 1 ) Starting IO pin assignment... Completed IO pin assignment. sroute -noBlockPins -noPadRings **WARN: (ENCSR-4053): SRoute option "-noBlockPins" is obsolete and has been replaced by "-connect". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use "-connect". **WARN: (ENCSR-4053): SRoute option "-noPadRings" is obsolete and has been replaced by "-connect". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use "-connect". *** Begin SPECIAL ROUTE on Mon Oct 4 16:46:11 2010 *** Sroute/fcroute version 8.1.46 promoted on 02/17/2009. SPECIAL ROUTE ran on directory: /home/bouldin/webhome/protected/651-hw6 SPECIAL ROUTE ran on machine: ada8.eecs.utk.edu (Linux 2.6.18-194.11.4.el5 Xeon 2.00Ghz) Begin option processing ... (from .sroute_13095.conf) srouteConnectPowerBump set to false (from .sroute_13095.conf) routeSpecial set to true (from .sroute_13095.conf) srouteConnectBlockPin set to false (from .sroute_13095.conf) srouteFollowCorePinEnd set to 3 (from .sroute_13095.conf) srouteJogControl set to "preferWithChanges differentLayer" (from .sroute_13095.conf) sroutePadPinAllPorts set to true (from .sroute_13095.conf) sroutePreserveExistingRoutes set to true End option processing: cpu: 0:00:00, real: 0:00:00, peak: 697.00 megs. Reading DB technology information... Finished reading DB technology information. Reading floorplan and netlist information... Finished reading floorplan and netlist information. Read in 22 layers, 10 routing layers, 1 overlap layer Read in 33 macros, 2 used Read in 10 components 10 core components: 0 unplaced, 10 placed, 0 fixed Read in 8 physical pins 8 physical pins: 0 unplaced, 8 placed, 0 fixed Read in 8 nets Read in 2 special nets Read in 28 terminals Begin power routing ... **WARN: (ENCSR-1256): Net vdd does not have CORE class pad pins to be routed. Please check net list or port class. Net vdd does not have AREAIO class pad pins to be routed. Please check net list or port class. **WARN: (ENCSR-1256): Net gnd does not have CORE class pad pins to be routed. Please check net list or port class. Net gnd does not have AREAIO class pad pins to be routed. Please check net list or port class. **WARN: (ENCSR-511): instance I0 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I1 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I2 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I3 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I4 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I5 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I6 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I7 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I8 is not placed in the correct row, followpin rail may not be generated correctly for it. **WARN: (ENCSR-511): instance I9 is not placed in the correct row, followpin rail may not be generated correctly for it. CPU time for FollowPin 0 seconds CPU time for FollowPin 0 seconds Number of IO ports routed: 0 Number of Stripe ports routed: 0 Number of Core ports routed: 0 Number of Followpin connections: 2 End power routing: cpu: 0:00:00, real: 0:00:00, peak: 703.00 megs. Begin updating DB with routing results ... Updating DB with 8 io pins ... Updating DB with 14 via definition ... sroute: Total CPU time used = 0:0:0 sroute: Total Real time used = 0:0:0 sroute: Total Memory used = 1.18 megs sroute: Total Peak Memory used = 328.92 megs addFiller -cell FILL -prefix FILL -fillBoundary Design contains fractional 20 cells. *INFO: Adding fillers to top-module. *INFO: Added 0 filler inst of any cell-type. globalNetConnect vdd -type tiehi globalNetConnect vdd -type pgpin -pin vdd -override globalNetConnect gnd -type tielo globalNetConnect gnd -type pgpin -pin gnd -override globalDetailRoute globalDetailRoute #Start globalDetailRoute on Mon Oct 4 16:46:11 2010 # #cpu time = 00:00:00, elapsed time = 00:00:00, memory = 328.00 (Mb) #WARNING (NRDB-976) The step 0.280000 for preferred direction tracks is smaller than the pitch 0.285000 for LAYER metal4. This will cause routability problems for NanoRoute. #WARNING (NRDB-976) The step 0.280000 for preferred direction tracks is smaller than the pitch 0.285000 for LAYER metal6. This will cause routability problems for NanoRoute. #WARNING (NRDB-976) The step 0.840000 for preferred direction tracks is smaller than the pitch 0.855000 for LAYER metal8. This will cause routability problems for NanoRoute. #WARNING (NRDB-976) The step 1.680000 for preferred direction tracks is smaller than the pitch 1.710000 for LAYER metal10. This will cause routability problems for NanoRoute. #NanoRoute Version v09.12-s013 NR100629-2344/USR64-UB #WARNING (NREX-28) The height of the first routing layer metal1 is 0.000000. It should be larger than 0.000000 #WARNING (NREX-29) The metal thickness of routing layer metal1 is 0.000000. It should be larger than 0.0. Add this to the technology information for better accuracy. #WARNING (NREX-30) Please also check the height and metal thickness values for the routing layers heigher than routing layer metal1 #WARNING (NREX-4) No Extended Cap Table was imported. Not enough process information was provided either and default Extended Cap Table database will be used. #Merging special wires... #Number of eco nets is 0 # #Start data preparation... #Auto generating G-grids with size=15 tracks, using layer metal2's pitch = 0.145. #Using automatically generated G-grids. # #Data preparation is done on Mon Oct 4 16:46:12 2010 # #WARNING (NRGR-30) There is no routing track on layer metal10 in preferred Y routing direction. #Analyzing routing resource... #Routing resource analysis is done on Mon Oct 4 16:46:12 2010 # # Resource Analysis: # # Routing #Total %Gcell # Layer Direction Gcell Blocked # ------------------------------------------ # Metal 1 H 8 100.00% # Metal 2 V 8 0.00% # Metal 3 H 8 0.00% # Metal 4 V 8 0.00% # Metal 5 H 8 0.00% # Metal 6 V 8 0.00% # Metal 7 H 8 0.00% # Metal 8 V 8 0.00% # Metal 9 H 8 0.00% # Metal 10 V 8 0.00% # ------------------------------------------ # Total 80 10.00% # # # #cpu time = 00:00:00, elapsed time = 00:00:00, memory = 344.00 (Mb) # #start global routing iteration 1... #cpu time = 00:00:00, elapsed time = 00:00:00, memory = 344.00 (Mb) # #start global routing iteration 2... #cpu time = 00:00:00, elapsed time = 00:00:00, memory = 344.00 (Mb) # #start global routing iteration 3... #cpu time = 00:00:00, elapsed time = 00:00:00, memory = 344.00 (Mb) # # # Congestion Analysis: (blocked Gcells are excluded) # # OverCon # #Gcell %Gcell # Layer (1) OverCon # -------------------------------- # Metal 2 0(0.00%) (0.00%) # Metal 3 0(0.00%) (0.00%) # Metal 4 0(0.00%) (0.00%) # Metal 5 0(0.00%) (0.00%) # Metal 6 0(0.00%) (0.00%) # Metal 7 0(0.00%) (0.00%) # Metal 8 0(0.00%) (0.00%) # Metal 9 0(0.00%) (0.00%) # Metal 10 0(0.00%) (0.00%) # -------------------------------- # Total 0(0.00%) (0.00%) # # The worst congested Gcell overcon (routing demand over resource in number of tracks) = 1 # #Complete Global Routing. #Total wire length = 57 um. #Total half perimeter of net bounding box = 101 um. #Total wire length on LAYER metal1 = 0 um. #Total wire length on LAYER metal2 = 0 um. #Total wire length on LAYER metal3 = 57 um. #Total wire length on LAYER metal4 = 0 um. #Total wire length on LAYER metal5 = 0 um. #Total wire length on LAYER metal6 = 0 um. #Total wire length on LAYER metal7 = 0 um. #Total wire length on LAYER metal8 = 0 um. #Total wire length on LAYER metal9 = 0 um. #Total wire length on LAYER metal10 = 0 um. #Total number of vias = 43 #Up-Via Summary (total 43): # #----------------------- # Metal 1 22 # Metal 2 21 #----------------------- # 43 # #Max overcon = 0 track. #Total overcon = 0.00%. #Worst layer Gcell overcon rate = 0.00%. #Cpu time = 00:00:00 #Elapsed time = 00:00:00 #Increased memory = 1.00 (Mb) #Total memory = 344.00 (Mb) #Peak memory = 377.00 (Mb) # #Start Detail Routing. #start initial detail routing ... # number of violations = 1 #cpu time = 00:00:00, elapsed time = 00:00:00, memory = 350.00 (Mb) #start 1st optimization iteration ... # number of violations = 0 #cpu time = 00:00:00, elapsed time = 00:00:00, memory = 351.00 (Mb) #Complete Detail Routing. #Total wire length = 73 um. #Total half perimeter of net bounding box = 101 um. #Total wire length on LAYER metal1 = 3 um. #Total wire length on LAYER metal2 = 12 um. #Total wire length on LAYER metal3 = 59 um. #Total wire length on LAYER metal4 = 0 um. #Total wire length on LAYER metal5 = 0 um. #Total wire length on LAYER metal6 = 0 um. #Total wire length on LAYER metal7 = 0 um. #Total wire length on LAYER metal8 = 0 um. #Total wire length on LAYER metal9 = 0 um. #Total wire length on LAYER metal10 = 0 um. #Total number of vias = 57 #Up-Via Summary (total 57): # #----------------------- # Metal 1 28 # Metal 2 29 #----------------------- # 57 # #Total number of DRC violations = 0 #Total number of violations on LAYER metal1 = 0 #Total number of violations on LAYER metal2 = 0 #Total number of violations on LAYER metal3 = 0 #Total number of violations on LAYER metal4 = 0 #Total number of violations on LAYER metal5 = 0 #Total number of violations on LAYER metal6 = 0 #Total number of violations on LAYER metal7 = 0 #Total number of violations on LAYER metal8 = 0 #Total number of violations on LAYER metal9 = 0 #Total number of violations on LAYER metal10 = 0 #detailRoute Statistics: #Cpu time = 00:00:00 #Elapsed time = 00:00:00 #Increased memory = 1.00 (Mb) #Total memory = 345.00 (Mb) #Peak memory = 377.00 (Mb) # #globalDetailRoute statistics: #Cpu time = 00:00:00 #Elapsed time = 00:00:00 #Increased memory = 15.00 (Mb) #Total memory = 343.00 (Mb) #Peak memory = 377.00 (Mb) #Number of warnings = 9 #Total number of warnings = 9 #Number of fails = 0 #Total number of fails = 0 #Complete globalDetailRoute on Mon Oct 4 16:46:12 2010 # uiSetTool ruler *** Memory Usage v0.159.2.9 (Current mem = 348.625M, initial mem = 60.020M) *** --- Ending "Encounter" (totcpu=0:00:04.3, real=0:04:43, mem=348.6M) ---