Homework 9: Floorplanning and Clock Tree Synthesis Using Synopsys JupiterXT

Introduction

Part A

1. Setting up JupiterXT environment

Login in to ada3.eecs.utk.edu

Change to the /tmp directory: cd /tmp

Make a homework directory of your own: mkdir yourusername-hw9

Copy the tar file to the /tmp and expand it:

cp ~bouldin/webhome/protected/651-hw9.tar.gz /tmp/yourusername-hw9

cd yourusername-hw9; gunzip 651-hw9.tar.gz; tar -xvf 651-hw9.tar

cd 651-hw9/JXT/GRF2*

Note : During many of the steps in the HW below, the options window will have an 'OK' and 'Apply' button. Don't click Apply and then OK. It will perform the same operation again and is a waste of time, so just click OK.

Capture some screen shots as you go to prove that you completed this hw.

2. Start a JupiterXT session

tcsh
source setup.csh
cd JXT
bash
export SNPSLMD_LICENSE_FILE="27011@synopsys-lic.eecs.utk.edu"
JupiterXT &

3. Importing the design

4. Floorplanning and Power planning

Before we learn to perform the placement of the cells, we need to unplace them first. To do that, go to Floorplan -> Unplace Std Cells/HM. If you want to keep the Macro or Std Cell placement intact, check that option in the Unplace Cells window which comes up.
For this tutorial, you can leave that option and just click ok. Sometimes, the cell immedietly gives the unplaced view, and sometimes it doesn't. To see the unplaced cell, first save and close the cell using Cell -> Save and Cell -> Close and then open the cell again. It will show the unplaced view as shown below.
Capture a screenshot of that view.

After the design is loaded, you should see your core area of the chip. You can zoom in and out either by clicking on the buttons on the top left on the cell view or by Views -> desired zoom from options.
To get details of a block, press the "Query-Object" button on the cell view window and click on the desired block. The block details are displayed on the main window.

To view the object connections, go to Query -> Flyline/ Show Object Connections and click on the desired object. It is displayed as shown below

Plant the power rings by choosing Virtual Flat Flow -> Power -> rectangular rings. Change the width and the spacing of the ring if you want. You can leave everything else as default and click OK to add the ring.

Now, you can start moving the module guides into the chip core area.To move an object, go to Edit -> Move and select the block to move. In the move options window, select "check overlap" and "snap to flipchip grid" options.

5. Standard Cells Placement

6. Viewing the Placement Congestion Map

For best results, click on "Fit with margin" button (3rd row, 3rd column on the set of buttons next to cell view) and you can see all the congestions. The one along the edges is 1-D congestion and the blue marks inside are 2-D. If there are large areas of congestion due to std. cell placement, rerun the placement with higher congestion effort.

6. Clock Tree Synthesis (CTS)

Clock tree synthesis can improve the timing performance of a chip by carefully distributing clock signals to each synchronous pin, using balanced multilevel clock trees based on accurate layout information.
Setting Clock Tree Synthesis Common Options and Preparing Clocks
Select Refine Design > Refine Each Soft Macro–Clock Common Options.
The Clock Common Options dialog box appears. Select the options, or keep the default settings. Click OK.

Running Clock Tree Synthesis
Select Clock -> Clock Tree Synthesis.
Select the options you want or use default settings. By default, clock tree synthesis synthesizes clock trees under the worst-case operating condition. Click OK.
The operation takes a little while and once it is completed, you can view the floorplan and notice the changes due to clock tree synthesis between 2 blocks and also near the edges.

7. Power Network Synthesis (PNS)

Power network synthesis (PNS) offers advanced power planning technology and helps solve signal integrity problems without lengthy and tedious iterations. By performing power network synthesis, you can get preview an early power plan that lessens the chances of encountering electromigration and voltage drop problems later in the detailed power routing.

PNS is generally performed after placement because the cells are closer to the final placement so power network synthesis can do a better job of estimating power distribution before Power routing. You can also run power network synthesis before the placement is finalized and after the core is initialized.

To perform PNS, select Virtual Flat Flow -> Power -> Power net Synthesis. A window pops up.

For the P/G Nets box, click on Search and select VDD. Click on Synthesize power Pad option as shown in screenshot. This is required only for the 1st time and this will generate a vpad file in the JXT directory. Click on the Virtual pads button and select VDD there as well. For other options, you can change some or keep the default values. Click on OK.

Note: If you are still getting an error to add Virtual pads, go to Virtual Pads, click on Load and select the default.vpad file, it should display all the Virtual Pads for VDD and VSS. Then Click OK, and perform PNS. It has to work this time.

You can also perform Power Net Analysis by selecting Virtual Flat Flow -> Power -> Power net Analysis and check for Voltage drop and electromigration violations in your design.

8. Timing Report

The dialog box provides information about setup, hold, maximum transitions, and maximum capacitance constraints within the design. You can set options or keep default settings

You can extract a quick summary report for the current timing by selecting Max and Min next to Delay Type and selecting Max Trans and Max Cap under Report Constraints. You can also create a histogram (graphic representation) for setup and hold constraints, by selecting Show Histogram under Other Options.

Run the report and capture a screenshot

When its done, you can save and close the cell and exit JupiterXT.