ECE 652 PROJECT SLIDES - NARRATIVE

 

  1. Introduction and General Architecture of our System-on-a-Chip

  2. Data Encryption Standard (DES)

  3. DES Block Diagram

  4. DES Encryption Algorithm

  5. DES – Specifications

  6. DES Pre Layout Simulation

  7. RAM Block Diagram and RAM Specifications

  8. RAM Pre-Layout Simulation

  9. Complete Block Diagram

  10. Modules

  11. Working of Top Module

  12. Top Module Schematic

  13. Top Module Pre-Layout Simulation

  14. DES Post - Layout Simulation

  15. RAM Post - Layout Simulation

  16. Top Module Post - Layout Simulation

  17. DES on Xilinx’s Virtex 1000E

  18. Top Module on Virtex 1000E

  19. Top Module Specifications

  20. Summary

Introduction and General Architecture of our System-on-a-Chip:

System on a Chip (SoC) is an IC designed by switching together multiple stand-alone VLSI designs to provide full functionality for an application. System-on-a-Chip emphasizes the use of models called cores also called intellectual property (IP) block or virtual components or macros.

Available Pre-designed cores:                                              

                 1.Synthesizable high-level description language (HDL) form such as Verilog/VHDL - Soft Cores/Firm Cores

                 2.Optimized transistor-level layout such as GDSII - Hard Cores

In our project, we make use of HDL descriptions of existing IP blocks. The HDL descriptions were simulated to ensure the functionality and then synthesized to obtain the gate level netlist. The gate level netlist was then simulated using the back – annotated delays in the VHDL/Verilog netlist to ensure functionality and timing. The place and route was then performed using Silicon Ensemble, Cadence Virtuoso and Xilinx Virtex 1000E.

 The IP blocks used in this course project were,

We used the DES IP block and Asynchronous Dual Port Designware RAM for our project. The Leon Processor and all the IP blocks – FFT, DES, AES and the FIR are linked through the Advanced Microcontroller Bus Architecture (AMBA).

Data Encryption Standard (DES):

The Data Encryption Standard (DES) was developed by and IBM team in 1974 and then adopted in 1977 by the National Bureau of Standards now the National Institute of Standards and Technology (NIST). For DES, data are encrypted in 64-bit blocks using a 64-bit key. The algorithm transforms 64-bit input in a series of steps into a 64-bit output. The same steps with the same key can be used to reverse the encryption. Hence it is a Symmetric algorithm.

The DES (VHDL) code used in our project was developed by Chris Eilbeck and later modified by Xiaoquan Fu.

Advanced Encryption Standard (AES) was developed, as a more robust replacement for the Data Encryption Standard (DES). It is a symmetric algorithm using block encryption of 128 bits in size, supporting key sizes of 128, 192 and 256 bits, as a minimum.

DES Block Diagram:

The Data Encryption Standard (DES) IP uses two inputs: key (64 bits) and Plain Text (64 bits). It uses the DES Encryption Algorithm and encrypts the plain text using the key to give 64 bit ciphered text.

DES Encryption Algorithm:

The overall scheme for DES encryption is illustrated in the figure shown in the slide. There are two inputs to the encryption function: the plain text to be encrypted and the key. In this case the plain text and the key are 64 bits in length.

Looking at the left-hand side of the figure, we can see that the processing of the plaintext proceeds in three phases. First, the 64-bit plain text passes through an initial permutation that rearranges the bits to produce the permuted input. This is followed by a phase consisting of 16 rounds of the same function, which involves both permutation and substitution functions. The output of the last (sixteenth) round consists of 64 bits that are functions of the input plaintext and the key. The left and the right halves of the output are swapped to the preoutput. Finally, the preoutput is passed through a permutation that is the inverse of the initial permutation function to produce the 64-bit cipher text.

DES – Specifications:

 Input:

Output:

Clock Frequency – 10 MHz

DES Pre Layout Simulation: 

Key: 0000000000000000 (hex) Plaintext: 000000000000000 (hex) 

Expected ciphered text output: 8ca64de9c1b123a7 (hex)

The DES module was simulated to verify functionality and the screenshot that was obtained using ModelSim tools was captured. The input data shown in the above table are used as stimuli and the responses (ciphered text output) matches the expected value. This verifies the functionality of the DES module.

 RAM Block Diagram and RAM Specifications:

The Synopsys Designware's Asynchronous Dual Port RAM (DW_ram_r_w_a_dff_inst.vhd) was instantiated in our project for the Input and the Output RAM respectively. This RAM has the following features:

·         Parameterized Word Depth – This was set to 16 for our project

·         Parameterized Data Width – This was set to 32 bits for our project

·         Asynchronous Static Memory

Description of the Input RAM and the Output RAM

Input RAM

The Data Encryption Standard IP block requires the inputs: key (64 bit) and the plain text (64 bit) to be encrypted respectively. The function of the Input RAM is to store the input values in its contiguous locations. The RAM IP has a data width of 32 bits. Therefore, the key and plain text had to be stored as two words of 32 bits each in successive locations. In our case, the key was stored in locations “0000” and “0001” respectively and the plain text was stored in locations “0010” and “0011” respectively. This is for the first set of input data. For all the data, the same sequence is followed from location “0100" onwards. The controller (state machine) was implemented for two sets of input data. (Please refer to the User Guide for the usage of RAM signals).

Output RAM

The Data Encryption Standard IP block encrypts the plain text using the key input and computes the ciphered text (64 bits). The function of the Output RAM is to store the output values in its contiguous locations. The Output RAM IP uses a data width of 32 bits. Therefore, the ciphered text had to be stored as two words of 32 bits each in successive locations. In our case the ciphered text corresponding to the first set of input data would be stored in locations “0000” and “0001” respectively.

RAM Pre-Layout Simulation:

Pre Layout Simulation was done to verify the functionality of the Asynchronous Dual Port RAM. The data was written to the RAM locations using the RAM signals and then the data was read from the RAM to make sure that the reading and writing of data occurred. (Please refer to the User Guide for the usage of RAM signals). For example, input data, “00000000” (binary) was being written to the address location “000”. This is done when a low to high transition signal of inst_wr_n signal when the address and data are available on the respective buses. When reading from that location, the data “00000000” is present on the output data bus. 

Complete Block Diagram:

The data from other blocks in the SoC is written into the input RAM via the input RAM data write bus and the input ram write address bus. When all the data to be encrypted is written into the RAM the 'go' signal is made high. The ‘Reset’ Signal is used to initialize the addresses and the states in the controller state machine. The controller block of the system takes over the control and transfers the data to the DES block where the encryption begins. The output of the DES that is the ciphered text is read and written into the output RAM by the controller. This can be read by the other blocks of the SoC via the output RAM read bus. 

 Modules:

Modules used a combination of Verilog and VHDL. The following are our modules.

 Working of Top Module:

First the key and plain text are stored in the Input RAM. The controller module uses a state machine that goes through a sequence of states. Thus the data are fetched and transferred to the DES module inputs. The DES module encrypts the plain text using the key and computes the ciphered text.  After 16 clock cycles, the ciphered text is available at the output of the DES. The ciphered text is stored in the Output RAM.

Top Module Schematic:

The top module schematic was obtained using Mentor Graphics fpgadvpro.

Top Module Pre-Layout Simulation:

The Pre Layout Simulation was done for the entire module using Mentor Graphics ModelSim tools. The design was simulated at 10 MHz clock frequency. The stimuli were,

First set of data:

Second set of data:

The responses matched the expected results as per the DES Encryption Algorithm

 DES Post-Layout Simulation: 

Key: FEDCBA98765432190 (hex) Plaintext: FFFFFFFFFFFFFFFF (hex) 

Expected ciphered text output: 2A2BB00BDF97C2F2 (hex)

The DES gate level netlist was simulated to verify functionality and timing and the screenshot that was obtained using ModelSim tools was captured. It used the back-annotated delays from the standard delay format file (sdf file). The input data shown in the above table are used as stimuli and the responses (ciphered text output) matches the expected value. This verifies the functionality of the DES module.

RAM Post-Layout Simulation:

Post Layout Simulation was done to verify the functionality and timing of the Asynchronous Dual Port RAM synthesized netlist. The data was written to the RAM locations using the RAM signals and then the data was read from the RAM to make sure that the reading and writing of data occurred. (Please refer to the User Guide for the usage of RAM signals).

Top Module Post-Layout Simulation:

The Post Layout Simulation was done for the entire module using Mentor Graphics ModelSim tools. The design was simulated at 10 MHz clock frequency. The stimuli were,

First set of data:

Second set of data:

The responses agree with the pre layout simulation results and expected results as per the DES Encryption Algorithm  

DES on Xilinx’s Virtex 1000E:

The DES module is targeted to Xilinx's Virtex 1000E.

Synopsys's FPGA compiler was used to synthesize the DES module in order to target to the Xilinx' Chip.Synthesis results came out without any errors and the edif file was generated which had to entire design in Electronic data format.

Xilinx ISE 5.2i set of tools were used to do the mapping and place and route of the DES design onto Xilinx’s Virtex. There were no timing errors and the chip occupied the chip effectively.

 The following is the summary of the mapping :

 Mapping results :

           Logic Utilization:

Number of Slice Flip Flops: 512 out of 24,576 2%

Number of 4 input LUTs: 3,312 out of 24,576 13%

           Logic Distribution:

            Number of occupied Slices: 1,684 out of 12,288 13%

Number of Slices containing only related logic: 1,684 out of 1,684 100%

Number of Slices containing unrelated logic: 0 out of 1,684 0%

Total Number of 4 input LUTs: 3,312 out of 24,576 13%

Total equivalent gate count for design: 28,576 Peak Memory Usage: 102 MB

Top Module on Virtex 1000E

 The entire Top module was mapped to the Virtex chip with the DES and the RAM.

 Summary of mapping:

 Design Summary

  Number of Slices:              1,906 out of 12,288   15%

   Number of Slices containing unrelated logic:                0 out of  1,906    0%

   Total Number Slice Registers:    822 out of 24,576    3%

   Number used as Flip Flops:                  821

   Number used as Latches:                       1

   Number of 4 input LUTs:        3,651 out of 24,576   14%

 Total equivalent gate count for design:  33,093

Top Module Specifications

nChip Area = 1799728761600 sq. db  or (449932.1904 sq. microns)

nTransistor Count

n    95306 NMOS

n    94378 PMOS

nClock Frequency – 10 MHz

Summary

The project used the existing IP blocks such as the DES and RAM. A controller module (state machine) was written in Verilog to control the data input and output from the Input RAM and to the Output RAM respectively. It was interfaced with the other IP blocks. The Pre layout and Post Layout simulation results agree with the expected results. The Place and Route was successfully done using Silicon Ensemble, Cadence Virtuoso and Xilinx Virtex 1000E.