library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;                      -- AMBA Bus definitions




entity apb_slave is
  port (
    rst  : in  std_logic;               -- Reset Input for the module
    clk  : in  clk_type;                -- Clock Input for the module
    
    apbi : in  apb_slv_in_type;         -- Uses the AMBA APB Slave Input Signals
    apbo : out apb_slv_out_type        -- Uses the AMBA APB Slave Output Signals
    
    ); 
end apb_slave;


architecture rtl of apb_slave is
  -- The 2 32-bit registers in the design
  signal REG0 : std_logic_vector(31 downto 0) := (others => '0');
  signal REG1 : std_logic_vector(31 downto 0) := (others => '0');
  signal REG  : std_logic_vector(31 downto 0) := (others => '0');
  constant zero32 : std_logic_vector (31 downto 0):= "00000000000000000000000000000000";
 
  type block_data  is array (natural range <>) of std_logic_vector (31 downto 0);
  subtype block32_data is block_data (0 to 31);

  signal inputdata : block32_data;


begin  -- rtl

  regprocess: process(clk,rst)
  variable rdata : std_logic_vector(31 downto 0) := zero32;  -- 32-bit Read Data bus
 
begin  -- process regprocess

 if (rst = '0') then                    
    -- Clear the contents of the registers
    REG0 <= (others => '0');
    REG1 <= (others => '0');
    REG  <= (others => '0');

 elsif(clk'event and clk = '1') then 

  if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
    case apbi.paddr(4 downto 2) is
      when "000" =>
        REG0  <= apbi.pwdata(31 downto 0) + 1 ;
      when "010" =>     
        REG1 <= apbi.pwdata(31 downto 0);
      when "011" =>     
        REG <= apbi.pwdata(31 downto 0);
      when others => null;
    end case;   
  end if;

  rdata := (others => '0');             -- init

  case apbi.paddr(4 downto 2) is
    when "000" =>
       rdata := REG0 ;
    when "010" =>
       rdata    := REG1;
    when "011" =>
       rdata    := REG;
    when others => null;
  end case;
  
  

  apbo.prdata <= rdata;

end if;  
end process regprocess;
end rtl;