RESULTS
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Pre-Layout Simulation - ModelSim |
Layout - Silicon Ensemble |
Layout - Virtuoso |
Extracted View |
LVS |
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Pre-Layout Simulation - ModelSim |
Layout - Xilinx Virtex 1000e |
Post-synthesis - ModelSim |
Layout - Virtuoso |
Post-Layout Simulation - Modelsim |
Extracted View |
LVS |
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Pre-Layout Simulation Overall Waveform - ModelSim |
Pre-Layout Simulation RAM1, RAM2 data transfer - ModelSim |
Pre-Layout Simulation RAM2, RAM3 data transfer - ModelSim |
Pre-Layout Simulation Output from RAM3 - ModelSim |
Layout - Xilinx Virtex 1000e |
Post-synthesis Waveform Overall Waveform - ModelSim |
Post-synthesis Waveform RAM1, RAM2 data transfer - ModelSim |
Post-synthesis Waveform RAM2, RAM3 data transfer - ModelSim |
Post-synthesis Waveform Output from RAM3 - ModelSim |
Layout - Virtuoso |
Layout_Zoom - Virtuoso |
Post-Layout Simulation Overall Waveform - ModelSim |
Post-Layout Simulation RAM1, RAM2 data transfer - ModelSim |
Post-Layout Simulation RAM2, RAM3 data transfer - ModelSim |
Post-Layout Simulation Output from RAM3 - ModelSim |
Post-Layout Delay |
Schematic |