Working as a large team, the entire class undertook a system-on-chip (SoC) project.
Small groups of 2-3 students acquired existing virtual components or IP (intellectual
property) blocks, tested them in stand-alone mode, modified them as required and then
planned to integrate them into the SoC. Each block was
simulated using ModelSim, synthesized using Synopsys or Synplicity and
placed/routed using Cadence Silicon Ensemble (TSMC-0.18) and Xilinx PAR (Virtex 1000E).
The goal was to achieve post-layout simulation of the integrated SoC core by the end of the term
(with subsequent addition of pads and submission to MOSIS for fab). However, this was not
quite accomplished.
The SoC contains:
LEON CPU with AMBA Bus (sampath and pkurugan)
Analog front-end with sigma-delta converter (scterry and nislam)
FIR (nraghura and mdorai)
FFT (gabi and sirisha)
DES (agothan1, balash and sdevalap)
AES (ntiwari and rishi)
RAM (kpatel5, wala and sliu)
The following IP blocks were tested in stand-alone mode and then with input and output RAMs:
TEST-RAM, DES, AES, FIR, FFT, Analog.
Next, the TEST-RAM will be integrated with the LEON-AMBA-BUS section.
Next, each IP will be substituted for the TEST-RAM.
Finally, all IP will be integrated into the SoC simultaneously.
Each of the following groups reported on the items listed below. Homework tutorials were developed for cve, cocentric and systemc.
cve/seamless--ntiwari, rishi, wala
cocentric--mdorai, nraghura, sirisha
systemc--balash, agothan1 sdevalap
px--sliu, kpatel5
8051/leon--sampath, teja, gabi
analog--scterry, nislam