Synplicity Tools Demo
cp /sw/syndem/*.vhd .
synplicity_tools
synplify_pro&
Create a project:
File -> Build Project
verify file type is set to HDL files (img01) and click "Add All" then "OK"
You that now have built a basic project, you need to set the file heirarchy.
Click the + next to the VHDL folder. Now click Run-> Arrange VHDL Files
You can also manually do this by drag/drop. Lowest level at top of list (to be proc'd first), highest at bottom (to be proc'd last).
Now save your project by selecting File -> Save and name it tutorial
Check that the source compiles:
Press F7 or Run->Compile Only
Review and correct the errors shown in the errors tab of the TCL window. Double clicking on the error line brings up the source to the suspected line with the error.
Examine the RTL:
Click the RTL icon (img 02) to bring up a graphical high-level graphical model of the design. Use the zoom to zoom in on a block and use the push/pop to push into a block to see its internal workings. (img 03)
Close the RTL
Set constraints:
Start the SCOPE tools (Click Constraint icon or File->New->Constraint file). Accept the default settings by clicking OK.
--Set the clock constraint:
---Click the clocks tab
---Enable clock constraint by checking the enabled box next to clock
---Enter 170 in the frequency column and press return, the remaining columns are filled automatically
---Save the constraint file as tutorial.sdc and add the file to the project
---Close the contraint file editor
Set the device parameters:
Click the Implementation Options button, or choose Project->Implementation
Options.
Set the device to a Xilinx Virtex2 XC2V40-4 CS144
On the options tag select "Symbolic FSM Compiler" and "Resource Sharing", all others blank
On the Contraints tab make sure the constraint file (tutorial.sdc) is checked.
On the Implementation Results tab, make sure the "Write Vendor Constraint File" option is checked.
In the Timing Report tab, set the "Number of Critical Paths" to 25.
Do not change anything in the VHDL tab
Run Synthesys:
Click the RUN button in the project browser
Analysis:
Start the Technology Viewer (IMG 04)
This shows the design with cells directly mapped to the target technology. Browse the heirarchy on the left to see how selected primitives/modules are hightlighted in the tech view.
Timing:
Open the Log Watch window (View->[check]Log Watch Window)
In the Log Watch window, select the first log parameter and select "Worst Slack" to display the worst slack (IMG 05)
In the next two columns, display the estimated frequency and the requested frequency
To see detailed information about critical paths, open the log file (eight_bit_uc.srr) by selecting the view log button. Scroll down to Performance Summary and Worst Paths Information (ctrl-f for search).
This details the worst path, which we will make into a constrained critical path for resynthesis.
Analyze Critical paths in the Technology View:
Open the technology view window (img 04) and select the critical path icon (IMG 06). Zooming in on the nodes of the critical path, you will notice that the slack (second number) is negative, meaning you didn't meet the timing criteria.
We will handle this critical path by setting cycle constraints and resynthesizing.
Add new constraints:
Open the constraints file and under the Multi-cycle Paths tab add a constraint from the start point to the end point of the path detailed above. Set the cycles to 2. Ensure that the enabled column is checked.
Resynthesize and repeat adding multi-cycle path limits to 2 until the design meets the timing criteria (img 07)
Prepared by Jonathan Turnmire on October 19th, 2004