library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity card_generator is
  port(	in_clock : in std_logic;    
	in_random : in std_logic;
	out_card : out std_logic_vector(3 downto 0));
end card_generator;

architecture card_generator_arch of card_generator is 
begin
  process
    variable var_startup : natural range 0 to 1;
    variable var_sequence : std_logic_vector(3 downto 0);
    variable var_lfsr : std_logic_vector(7 downto 0);
    variable var_lfsr_next_bit : std_logic;
    variable var_temp : std_logic_vector(7 downto 0);
    variable var_deck : std_logic_vector(7 downto 0);
    variable var_count : natural range 0 to 104;
  begin
    wait until (in_clock'event) and (in_clock = '1');

    if (var_startup = 0) then
      var_startup := 1;
      var_sequence := "0000";
      var_deck := "00000001";
      var_count := 0;
    end if;

    if (in_random = '0') then
      var_sequence := var_sequence + 1;
      if (var_sequence = 14) then
	var_sequence := "0001";
      end if;
      out_card <= var_sequence;
    else 
      if (var_count = 0) then
	var_lfsr := var_deck;
	if (var_deck = "11111111") then
	  var_deck := "00000001";
	else
	  var_deck := var_deck + 1;
	end if;
      end if;

      for i in 1 to 8 loop
	if ((i=1) or (var_temp(7 downto 4) > 12)) then
	  var_lfsr_next_bit := var_lfsr(0) XOR var_lfsr(4) XOR
			       var_lfsr(5) XOR var_lfsr(7);
	  var_lfsr(7 downto 1) := var_lfsr(6 downto 0);
	  var_lfsr(0) := var_lfsr_next_bit;
	  var_temp := var_lfsr - 1;
	end if;
      end loop;
      out_card <= var_temp(7 downto 4) + 1;

      var_count := var_count + 1;
      if (var_count = 104) then
	var_count := 0;
      end if;
    end if;
  end process;
end card_generator_arch;