From dbouldin@utk.edu Mon Jan 22 21:33:44 2007
To: Steven Bunch <spaceman@utk.edu>
Subject: RE: HW 4 Errors

Steven:

Thanks for figuring these out.

As I recall, you served as our "pioneer" previously.

Your efforts are appreciated.  I'll post this much and
we'll see if someone else can get even further.

DWB.

>===== Original Message From Steven Bunch <spaceman@utk.edu> =====


- Figure 2 on page 3 does not match default values (use Figure 2 values or 
default?)

- Get the following error after running "vsim tb_func32 &" on page 4

	Unable to checkout a license. Make sure your license file environment 
variable (e.g., LM_LICENSE_FILE)
	is set correctly and then run 'lmdiag' to diagnose the problem .
	Unable to checkout a license.  Vsim is closing.
	** Fatal: Invalid license environment. Application closing.

- Worked after typing "mentor_tools" instead of "mentor_old_tools" on page 3

- Figure 3 on page 5 does not match default values (use Figure 3 values or 
default?)

- After running "dc_shell -f leon.dcsh > zm01.txt" on page 14 I get the 
following error

	analyze -f VERILOG -library WORK ../ram_tsmc25/dpram136x32_box0.v
	Running PRESTO HDLC
	Compiling source file ../ram_tsmc25/dpram136x32_box0.v
	Error:  Unable to open file `../ram_tsmc25/dpram136x32_box0.v': No such file 
or
	directory. (VER-292)
	*** Presto compilation terminated with 1 errors. ***

- These *.v files are actually located in the "../leon" directory as per the 
Black Box file generated from page 13
  Do the following to correct this error "cp ../leon/*.v ../ram_tsmc25/" and 
then run "dc_shell -f leon.dcsh > zm01.txt"

- Need to add the line "cp ../ram_tsmc25/dp*.v ." before "cd .." at the bottom 
of page 14

- I get the following error after running "vsim tb_func32 &" on pages 15 & 17

	# ** Fatal: (vsim-3693) The minimum time resolution limit (10ps) in the 
Verilog source is smaller than the one chosen for SystemC or VHDL units in the 
design. Use the vsim -t option to specify the desired resolution.
	#    Time: 0 ps  Iteration: 0  Instance: /tbleon File: 
/tnfs/home/sbunch/school/ECE652/hw4/soc/tbench/tbdef.vhd Line: UNKNOWN
	# FATAL ERROR while loading design
	# Error loading design

- Replace the "vsim tb_func32 &" command with "vsim -t ns tb_func32 &" to fix 
this problem.

- After running "vsim -t ns tb_func32 &" on page 17 I keep getting Warning 
messages like the following

	# ** Warning: (vopt-13) Recompile leon/work.dpram136x32_box0(dpram_rtl) 
because /mnt/sw/mentor/ModelSim_SE6.2a/modeltech/sunos5/../verilog.vl_types 
has changed.
	# ** Warning: (vopt-13) Recompile leon/work.dpram136x32_box1(dpram_rtl) 
because /mnt/sw/mentor/ModelSim_SE6.2a/modeltech/sunos5/../verilog.vl_types 
has changed.
	# ** Warning: (vopt-13) Recompile leon/work.ram2048x32_box0(ram_rtl) because 
/mnt/sw/mentor/ModelSim_SE6.2a/modeltech/sunos5/../verilog.vl_types has 
changed.
	# ** Warning: (vopt-13) Recompile leon/work.ram256x27_box0(ram_rtl) because 
/mnt/sw/mentor/ModelSim_SE6.2a/modeltech/sunos5/../verilog.vl_types has 
changed.

- Then I get an Error loading the design.  I am not sure how to fix this 
problem.