** Generated for: hspiceD
** Generated on: Aug 25 21:47:26 2010
** Design library name: ktham_lib
** Design cell name: INVX1_tb
** Design view name: schematic


.TRAN 10e-12 200e-9 START=0.0

.OP

.TEMP 25
.OPTION
+    ARTIST=2
+    INGOLD=2
+    PARHIER=LOCAL
+    PSF=2
.INCLUDE "/sw/cadence/FreePDK45-1.3/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTL.inc"
.INCLUDE "/sw/cadence/FreePDK45-1.3/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTL.inc"

.include "INVX1.pex.netlist.pex"


** Library name: ktham_lib
** Cell name: INVX1
** View name: schematic
.subckt INVX1  A GND VDD Y
* 
* Y     Y
* VDD   VDD
* GND   GND
* A     A
MM1 N_Y_MM1_d N_A_MM1_g N_GND_MM1_s N_GND_MM1_b NMOS_VTL L=5e-08 W=2.5e-07
+ AD=2.625e-14 AS=2.625e-14 PD=7.1e-07 PS=7.1e-07
MM0 N_Y_MM0_d N_A_MM0_g N_VDD_MM0_s N_VDD_MM0_b PMOS_VTL L=5e-08 W=5e-07
+ AD=5.25e-14 AS=5.25e-14 PD=1.21e-06 PS=1.21e-06
*

.include "INVX1.pex.netlist.INVX1.pxi"

.ends INVX1
** End of subcircuit definition.

** Library name: ktham_lib
** Cell name: INVX1_tb
** View name: schematic
xi0 net5 net4 net3 net6 INVX1
v1 net4 0 DC=0
v0 net3 0 DC=1
v2 net5 0 PWL 0 0 100e-9 0 101e-9 1 TD=0
.END