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Automatic Test Pattern generation using Synopsys TEtraMax
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(a) Invoke TetraMax in the shell mode by typing
    tmax -s
    This opens tetramax in the build mode and the following commands have to be typed in the BUILD> command prompt.
    
(b) Keep track of all the messages generated by the tool and do not exit if there are minor warnings.
    set messages log tmax_cmds.log –replace; set commands noabort

(c) Read the netlist and the verilog Library modules used to map Leon and other IP cores with library of standard cells.
    read netlist -library /home/ksundar1/public_html/verilog/ibm18.v; read netlist leon_test.v

(d) After reading in the library modules and the design netlist, report a summary of any undefined modules or errors encountered.
    report modules –summary
    report modules -error 
    report modules –undefined

(e) Define all the RAM modules as black box because certain modules are not referenced properly which will not allow to build the design.
    set build -black_box ram32x30_inst
    set build -black_box dpram136x32_inst
    set build -black_box ram256x32_inst

(f) Build the ATPG design model for Leon. This command builds the in-memory simulation model from the design modules that have been read in.
    run build_model leon
    Tetramax enters the DRC mode once the simulation model is built. The next few commands have to be entered in the DRC> command prompt.

(g) Set the DRC(Design Rule Check) parameters and perform Design Rule Checking, which is required to enter the TEST command mode, 
    where test generation and fault simulation may be performed.
    set drc -allow_unstable_set_resets; run drc leon_test.spf
    The next set of commands have to be entered in the TEST> command prompt.

(h) Report all the warnings and violations to a file for future reference.
    report rules -fail > leon_atpg.rpt; report violations -all > leon_atpg.rpt

(i) Specify the type of fault model to be used for pattern generation and create a list of fault sites for pattern generation. 
    Set the parameters that control the ATPG process including the coverage required.
    set faults -model stuck; add faults -all
    set atpg -merge high -abort_limit 90 -full_seq_atpg -coverage 100

(j) Generate test patterns for the set of fault sites created above, following the default sequence which is basic scan 
    followed by full-sequential ATPG. Run pattern compression to reduce the number of patterns by eliminating the unnecessary 
    patterns, which is determined by tetramax by performing a fault simulation of the current patterns.
    run atpg –auto; run pattern_compression 1

(k) Write out the test patterns in STIL format (the format recognized by Automated Test Equipment ATE), as well as verilog format. 
    The fault report is also written out for future reference.
    write faults leon_faults.rpt -all –replace
    write patterns leon_test_tb.v -replace -internal -format verilog_single_file -serial
    write patterns leon_test_tb.stil -internal -format stil –replace
    exit