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Static Timing Analysis using Synopsys PrimeTime
*************General Algorithm*****************
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(a) PrimeTime can be invoked in the shell mode by typing
    pt_shell
(b) Read the desing
    read_verilog <filename.v>
(c) Link the design to the library
    link_desingn <design module name>
(d) Specify the clock for the design. The name should match the clock name specified in the design and during synthesis.
    create_clock -period <period> -waveform {<First Transition> <Second Transition>} {<Clock name>}
(e) Primtime can be configured to output the critical paths in a text format. However, TetraMax (ATPG tool) requires the paths
    in a different format. So, a TCL procedure (write_delay_paths) has been supplied by TetraMax to produce the PrimeTime output in 
    a TetraMax acceptible format. This has been defined in the file pt2tmax.tcl
    source /sw/Synopsys_2005.09/auxx/syn/tmax/pt2tmax.tcl (if you use synopsys_latest_tools)
    source /sw/synopsys/auxx/syn/tmax/pt2tmax.tcl (if you use synopsys_tools)
(f) Output the critical paths
    write_delay_path -slack 15 -max_paths 100 -nworst 1 -clock <Clock name> <outfilename>.list
    // -slack <crit_time> : Writes paths with slacks less than <crit_time>.
    // -max_paths <num_paths> : Specifies the max number of paths to be written.
    // -nworst <num_per> : Specifies number of paths to each end point, Default=1.
    // -clock <clock_name> : Limits paths to <clock_name> domain.
    // -IO : writes I/o paths. Defaultis to only write internal paths.