#!/usr/bin/csh -f

source ~cad/.cshrc
mentor_tools

vlib XilinxCoreLib
vlib work
vmap XilinxCoreLib /sw/xilinx-libs/Xilinx6.3i/vhdl/mti_se/XilinxCoreLib

# The following commands are associated with compiling the RAM which has been generated using Xilinx's Coregen

vcom -work work dpram256_64.vhd  # RAM module
vcom -work work parith.vhd       # Parithmetic Module
vcom -work work pcore.vhd	 # Top Module
vcom -work work tb.vhd		 # Test Bench

# Simulating using ModelSim

 vsim  -coverage tb  -do  wave.do stim.do 

# vsim - Command to open Modelsim 
# wave.do - File that opens Parith and Pcore signals in Modelsim
# stim.do - File to run the Simulation