library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity parith is
port (
	clk: in std_logic;
	rst: in std_logic;
	addr: out std_logic_vector(7 downto 0);
	din: out std_logic_vector(63 downto 0);	-- write to block ram
	dout: in std_logic_vector(63 downto 0);	-- read  to block ram
	we: out std_logic;						-- write enable
	start: in std_logic;
	finish: out std_logic
);
end parith;

architecture rtl of parith is

signal state : std_logic_vector(3 downto 0);
signal idx: std_logic_vector(7 downto 0);

signal buf1: std_logic_vector(63 downto 0);
signal buf2: std_logic_vector(63 downto 0);
signal ans: std_logic_vector(63 downto 0);


begin

-- this core retreive two data from block ram and do are opereation OR
process (clk, rst)
begin

if (rst = '1') then
	state <= "0000";
	finish <= '0';
elsif (clk = '1' and clk'event)  then

-- state machine

	if (start = '1') then
		if (state = "0000") then
			state <= "0001";
			finish <= '0';
		end if;
	end if;

	if (state = "0001") then
		idx <= "00000000";
		state <= state + 1;
	elsif (state = "0010") then 
		idx <= "00000001";
		state <= state + 1;
	elsif (state = "0011") then 
		buf1 <= dout;
		state <= state + 1;
	elsif (state = "0100") then
		buf2 <= dout;
		state <= state + 1;
	elsif (state = "0101") then
		idx <= "00000111";	
		we <= '1';
		state <= "0110";
		finish <= '1';
	else
		we <= '0';
	end if;

end if;
end process;

addr <= idx;
ans <=  buf1 or buf2;
din <= ans;

end rtl;