-- Pcore Wrapper
-- Author: Ho Chun Hok
--         Graduate Student
--         The Computer Science and Engineering Department
--         The Chinese University of Hong Kong
--  email: chho2@cse.cuhk.edu.hk

-- Modified by Mahesh Dorai
-- email : mdorai@utk.edu

-- The Pcore is the module that encapsulates all the componens that one uses in his Pilchard overall design.
-- In this example, the other two components namely - the dpram256_64 and the parith are wrapped using the Pcore
-- interface.A Register capability is also extended to the existing pilchard framework to make the user aware of using
-- registers. 

-- The parith module on the other hand, is rather simple and it seres as the main arbitration machine to talk 
-- to.from the Dual Port RAM.  The start signal
-- is high for a cycle while writing anything to the address location 255. In order that we trigger the state machine that
-- is needed to start the operations of reading from the Dual Port RAM, we simply make the write signal high while 
-- simulateneously addressing the location = "11111111".

-- The finish signal as the name suggests is to indicate that the process of OR'ing the two numbers is done and that the 
-- value can now be read from the location the the signal "ans" has been written to.

-- Te address 255 is a special access location, by means of which you can trigger the circuit(state machine) to start. 
-- In the code for pcore.vhd, you will find lines commented lines that invole regisers. You can ignore them for the moment.

-- These registers can be later used for larger designs for the purpose of debugging. 

-- Even in the C code, you will find a value "reg" being read out. You may safely ignore the value of "reg" when you
-- read the final output from the Pilchard.

-- The Parith operates on the divided clock. Please look at the port maps in Pocre to understand mapping of the two
-- clocks that are provided in the design.
-- By changing the last line, the designer can choose either system clock (~100-133MHz) or the divided clock (clkdiv), 
-- The default is divided clock, which is generally half of the system clock, clkb <= clkdiv;

-- To get more informatio on the clock divisions, please refer pilchard.vhd. But DO NOT modify the Pilchard.vhd


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pcore is
port (
	clk: in std_logic;
	clkdiv: in std_logic;
	rst: in std_logic;
	read: in std_logic;
	write: in std_logic;
	addr: in std_logic_vector(13 downto 0);
	din: in std_logic_vector(63 downto 0);
	dout: out std_logic_vector(63 downto 0);
	dmask: in std_logic_vector(63 downto 0);
	extin: in std_logic_vector(25 downto 0);
	extout: out std_logic_vector(25 downto 0);
	extctrl: out std_logic_vector(25 downto 0) );
end pcore;


architecture syn of pcore is
component dpram256_64
	port (
	addra: IN std_logic_VECTOR(7 downto 0);
	clka: IN std_logic;
	dina: IN std_logic_VECTOR(63 downto 0);
	douta: OUT std_logic_VECTOR(63 downto 0);
	wea: IN std_logic;

	addrb: IN std_logic_VECTOR(7 downto 0);
	clkb: IN std_logic;
	dinb: IN std_logic_VECTOR(63 downto 0);
	doutb: OUT std_logic_VECTOR(63 downto 0);
	web: IN std_logic);
end component;

component parith
port (
	clk: in std_logic;
	rst: in std_logic;
	addr: out std_logic_vector(7 downto 0);
	din: out std_logic_vector(63 downto 0);
	dout: in std_logic_vector(63 downto 0);
	we: out std_logic;
	start: in std_logic;
	finish: out std_logic
);
end component;

signal addrb:std_logic_VECTOR(7 downto 0);
signal clkb: std_logic;
signal dinb: std_logic_VECTOR(63 downto 0);
signal doutb: std_logic_VECTOR(63 downto 0) := 
"0000000000000000000000000000000000000000000000000000000000000000";
signal web: std_logic;
signal start: std_logic;

signal read_latch: std_logic;
signal addr_latch: std_logic_vector(7 downto 0);
signal finish: std_logic;


signal bram_dout : std_logic_VECTOR(63 downto 0);

--debug signal
signal  start_debug:std_logic;
signal  web_debug:std_logic;

--register interface
--signal reg0: std_logic_VECTOR(31 downto 0);

begin

ram0:dpram256_64 port map  (
	addra	=> addr(7 downto 0),
	clka	=> clk,
	dina	=> din,
	douta	=> bram_dout,
	wea	=> write,

	addrb	=> addrb,
	clkb	=> clkb,
	dinb	=> dinb,
	doutb	=> doutb,
	web	=> web
);

parith0: parith port map (
	clk	=> clkb,
	rst	=> rst,
	dout	=> doutb,
	start	=> start_debug,

	addr	=> addrb,
	din	=> dinb,
	we	=> web,
	finish	=> finish 
);


process(clk,rst)
begin
if (rst = '1') then
	start_debug <= '0';
	web_debug <= '0';
elsif (clk'event and clk ='1') then
	addr_latch <= addr(7 downto 0);
	read_latch <= read;
	start_debug <= start_debug or start;
	web_debug <= web_debug or web;
end if;
end process;


--reg0(0) <= finish;
--reg0(1) <= start_debug;
--reg0(2) <= start;
--reg0(3) <= web_debug;
--reg0(4) <= web;
--reg0(30 downto 5) <= (others => '1');
--reg0(31) <= '0';

--dout(31 downto 0) <= 	reg0 when addr_latch(7 downto 0) = "11111111" 
--else bram_dout(31 downto 0);
dout(31 downto 0) <= bram_dout(31 downto 0);
dout(63 downto 32) <= bram_dout(63 downto 32);

start <= '1' when (write = '1' and addr(7 downto 0) = "11111111")
	else '0';

-- Define the Design Processing Clock
clkb <= clkdiv;


end syn;