library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tb is
end tb;

architecture syn of tb is

component pcore 
port (
	clk: in std_logic;
	clkdiv: in std_logic;
	rst: in std_logic;
	read: in std_logic;
	write: in std_logic;
	addr: in std_logic_vector(13 downto 0);
	din: in std_logic_vector(63 downto 0);
	dout: out std_logic_vector(63 downto 0);
	dmask: in std_logic_vector(63 downto 0);
	extin: in std_logic_vector(25 downto 0);
	extout: out std_logic_vector(25 downto 0);
	extctrl: out std_logic_vector(25 downto 0)
);
end component;

signal clk: std_logic;
signal clkdiv: std_logic;
signal reset: std_logic;
signal read: std_logic;
signal write: std_logic;
signal addr: std_logic_vector(13 downto 0);
signal din: std_logic_vector(63 downto 0);
signal dout: std_logic_vector(63 downto 0);
signal dmask: std_logic_vector(63 downto 0);
signal extin: std_logic_vector(25 downto 0);
signal extout: std_logic_vector(25 downto 0);
signal extctrl: std_logic_vector(25 downto 0);

begin


pcore0: pcore port map(
clk, clkdiv, reset, read, write, addr, 
din, dout, dmask, extin, extout, extctrl
);

process
begin

reset <= '1';
clk <= '0';
wait for 100 ns;

loop
	reset <= '0';
	clk <= '1';
	wait for 50 ns;
	clk <= '0';
	wait for 50 ns;
end loop;
end process;

process (clk, reset)
begin
if reset = '1' then
	clkdiv <= '0';
elsif clk'event and clk = '1' then
	clkdiv <= not clkdiv;
end if;
end process;

process
begin
read <= '0';
write <= '0';
addr <= "00000000000000";

wait for 200 ns;
read <= '0';

--write <= '1'; addr <= (others => '0'); 
--din <= 
--"0000000000000000000000000000000011111111111111111110111011101110";
--wait for 100 ns;

--write <= '1'; addr(7 downto 1) <= (others => '0'); addr(0) <= '1';
--din <= 
--"0000000000000000000000000000000000000000000000000001000100010001";
--wait for 100 ns;

write <= '1'; addr <= (others => '0');
din <= "1111111011111110000000001010101011111111111111110000000000000000";
wait for 100 ns;

write <= '1'; addr(7 downto 1) <= (others => '0'); addr(0) <= '1';
din <= "0001000100010001000000000000000000000000000000000001000100010001";
wait for 100 ns;

write <= '1'; addr(7 downto 0) <= (others => '1'); 
din <= "0000000000000000000000000000000000000000000000000000000000000000";
wait for 100 ns;

write <= '0'; addr(7 downto 0) <= (others => '1');
din <= "0000000000000000000000000000000000000000000000000000000000000000";
wait for 200 ns;



end process;



-- dummy signal
extin <= (others => '0');
dmask <= (others => '0');
end syn;