You can use the existing cells in the IIT library instead of
the ones generated in Homework_6.
Each student should develop a macro which incorporates a mixture
of the cell groups listed below using:
at least two instances each of both cells from group-a,
at least two cells from group-b,
at least two cells from group-c and
at least one cell from group-d.
Thus, the total complexity will be a minimum of 44 W.
W---Cell
--------
group-a:
3--NAND2
3--NOR2
group-b:
4--AND2
4--AOI21
4--NAND3
4--OAI21
4--OR2
group-c:
6--MUX2
7--XNOR2
7--XOR2
8--NOR3
group-d:
10-HA
15-FA
Project Schematics:
/home/username/public_html/651proj.gif
adeebndennis
darren
sfields1
gilbert
robertg
jjeon
tmarwah
matthews
nmichou
jpendlet
ishaik
turnmire
vprasad
jwhite25
dziemian
Compose your schematic at both the cell-level and fet-level. Determine the truth table for your macro. Perform pre-layout VerilogXL simulation. Perform pre-layout Spectre simulation. Generate 3 standard-height layouts that are compatible with the IIT-AMI04 library: (a) auto-cell using silicon ensemble (like hw6a) (b) auto-fet using progen (like hw8) (c) manual-fet (like hw6b) (try to use fewer W grids than the auto-fet layout) For each layout, perform DRC and LVS and post-layout Spectre simulation. Add shaping inverters and 4 load-chains (like hw4) to all 3 layouts and perform post-layout Spectre simulation with shaping/loading. Make a table comparing the three layouts in terms of area (W horizontal grids) and delay (fan-out-4) but don't count the area/delay of the shaping/loading. Compare the quality of the results and the design time required for these methods. Prepare your presentation and final report by capturing gif files to illustrate the layouts and simulations. Include a narrative description of your project on your web site in an HTML report. A partial report can be used for each student's presentation in class on 11/30/Tuesday. ---- All of the layouts should be the same height. SE will definitely use the standard height. Adjust "rowu" and "a" to make it come out as a single row with no fill (if possible). FINIT FLOORPLAN rowu 0.90 rowsp 0 blockhalo 0 f a 1.1 You can view the result immediately using "seultra" before importing the layout into icfb. If Progen does not give you the 20-lambda height, then use the -f or folding option. Progenesis does NOT use logic simplification and you should not either. All of the layouts should conform to the grid and be an integer multiple of 8-lambda (1.6u) in width. The report should show the schematics, pre and post simulations, layouts and LVS results. Also, include a table comparing the 3 layouts in terms of W, delay and design time. This table should be shown during your presentation on Tuesday. ---- Signup for a project checkoff on 12/1/Wed in the 501 Ferris Hall lab. A sample report can be found here. This report was prepared by first copying a LATEX source file (/usr/cad/course/report/report.tex) and editing it.
Next, type: latex report.tex twice.
To generate the postscript version, type: dvips -o report.ps report.dvi
The output can be viewed on the screen by typing: ghostview report.ps &
To generate the HTML version, just type: latex2html report.tex Pairings for MOSIS submissions: To be determined
MOSIS Status (T51X) U. Mass Course Penn State Projects Universities using Cadence