Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/mojo_top/spi |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2012-11-06T11:19:28 |
PROP_intWbtProjectID=F04BE7BB4526104AA483BCD2B63930B5 |
PROP_intWbtProjectIteration=33 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.spi |
PROP_xilxBitgCfg_GenOpt_Compress=true |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=false |
PROP_DevFamily=Spartan6 |
PROP_ibiswriterOutputFile=pwm_top |
PROP_xilxBitgCfg_GenOpt_BinaryFile=true |
PROP_DevDevice=xc6slx9 |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=tqg144 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=Verilog |
PROP_netgenPostMapSimModelName=pwm_top_map.v |
PROP_netgenPostParSimModelName=pwm_top_timesim.v |
PROP_netgenPostSynthesisSimModelName=pwm_top_synthesis.v |
PROP_netgenPostXlateSimModelName=pwm_top_translate.v |
FILE_UCF=1 |
FILE_VERILOG=4 |