mojo_top Project Status (11/14/2016 - 10:32:38)
Project File: PWM_Test.xise Parser Errors: No Errors
Module Name: mojo_top Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
67 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 11 11,440 1%  
    Number used as Flip Flops 11      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 28 5,720 1%  
    Number used as logic 27 5,720 1%  
        Number using O6 output only 19      
        Number using O5 output only 7      
        Number using O5 and O6 1      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 8 1,430 1%  
Number of MUXCYs used 12 2,860 1%  
Number of LUT Flip Flop pairs used 28      
    Number with an unused Flip Flop 17 28 60%  
    Number with an unused LUT 0 28 0%  
    Number of fully used LUT-FF pairs 11 28 39%  
    Number of unique control sets 3      
    Number of slice register sites lost
        to control set restrictions
21 11,440 1%  
Number of bonded IOBs 11 102 10%  
    Number of LOCed IOBs 11 11 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 1 4 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.63      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Nov 14 10:32:03 2016064 Warnings (0 new)1 Info (1 new)
Translation ReportCurrentMon Nov 14 10:32:08 2016001 Info (0 new)
Map ReportCurrentMon Nov 14 10:32:15 2016008 Infos (0 new)
Place and Route ReportCurrentMon Nov 14 10:32:23 201603 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentMon Nov 14 10:32:27 2016003 Infos (0 new)
Bitgen ReportCurrentMon Nov 14 10:32:35 2016001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Nov 14 10:32:35 2016
WebTalk Log FileCurrentMon Nov 14 10:32:38 2016

Date Generated: 11/14/2016 - 10:32:38