ECE255 Intro. to Logic Design, Fall 2010

Here's a pdf file of the syllabus. syl255F10.pdf

The following files can be copied when needed for the labs. They will be explained on the lab handouts.

You can edit this file to define the "User Constraints" in your labs. This *.ucf file tells the FPGA which of its I/O pins to connect to LEDs, switches and pushbuttons, 7-segment displays, and the clock (the on-board oscillator) on the BASYS board. You must delete or comment-out the lines in this file for all pins not explicitly used in your design. basys.ucf

Here're the vhdl code and bit files for Lab1. The vhdl file is plain text but THE BIT FILE IS NOT PLAIN TEXT. lab1.vhd lab1.bit

Here's the vhdl file for Lab3. CDiv.vhd

Here's the vhdl file for Lab4. DeBounce.vhd