Macro and Leafcell Properties
A macro consists of two or more leafcells.
A soft-macro can be "hypenated" or decomposed for global optimization
whereas a hard-macro or leafcell is fixed to preserve area/delay.
This semester we will compare 3 methods for implementing layouts:
2009-homework_6
Encounter Reference Manual (10 MByte pdf)
Layout with cells placed and then with 4 metal layers routed:
General Procedure
A. Invoke virtuoso to draw a schematic which uses multiple leaf_cells.
(or synthesize using Synopsys Design Compiler.)
B. Generate the net-list for HSPICE and simulate.
C. Generate the structural verilog net-list from the schematic or the
synthesizer or manually.
Note that the structural verilog for each standard cell (with timing)
is included in:
/sw/cadence/FreePDK45-1.3/osu_soc/lib/files/gscl45nm.v
where * = AND2X1, FAX1 etc.
D. Use SOC_Encounter to perform placement and routing.
Execute the following:
1. login to ada8.eecs.utk.edu
2. cp ~bouldin/webhome/protected/651-hw6.tar.gz .
3. gunzip 651-hw6.tar.gz; tar -xvf 651-hw6.tar
4. cd 651-hw6
You should have the following files:
adder4.v
circuit.v
encounter.conf
multiplyadd.v
nand2.v
parta1.tcl
parta2.tcl
parta3.tcl
partb1.tcl
partb2.tcl
partb3.tcl
partc.tcl
results.html
source4encounter
Note parta schematic
Note in parta1.tcl: floorplan -r 0.5 1.0
(Floorplan options: aspect ratio of H/W; core utilization)
5. source source4encounter
6. encounter -init parta1.tcl
7. In the graphical window, add rulers and save the layout as "parta1.jpg".
8. Then, type exit in the terminal window:
encounter 1> exit
9. Rename the log file as "parta1.log".
10. Continue for the other parts below.
For partb, cp adder4.v circuit.v
For partc, cp multiplyadd.v circuit.v
etc.
11. Post your hw6-results on your protected webpage.
12. Fill in the missing entries by looking in the log file.
Part D (Your own unique circuit):
Draw a schematic consisting of multiple instances of at least three different OSU standard cells
(with a complexity of about 50 fets) plus two shaping inverters on one input
and a fanout of 4 inverters on one output.
Create the structural verilog netlist. If necessary, copy partb.v to partd.v
and edit to produce the structural verilog netlist.
Perform pre-layout simulation using HSPICE.
Post your partd.v, HEIGHT, WIDTH, etc. and simulation results on your protected website.
Try various floorplans to achieve a near fully utilized one-row solution
and a near fully utilized two-row or three-row solution.
Use a ruler to indicate the dimensions of each solution.
Capture each result that you try (even the ones that are not fully utilized)
and post the layout images on your protected webpage.
Add rows and links to the results table as needed.
Update hw.html
