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User |
Guide |
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Working
of the System. |
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As
already explained the IP block consists of an Input RAM , Output RAM
and the DES. The data to be encrypted is written into the input RAM
and when the ‘go’ signal is made high the data in the Input RAM is
encrypted and written to the Output RAM.
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Description
of the signals
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inst_test_clk
– Clock Signal to all the blocks , 10 MHz
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A
clock of 5MHz is to be supplied to this pin
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inst_wr_addr
(4 bit , expandable to 8bit) – Input RAM Write Address
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This
is used to supply the write address to the input RAM
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inst_data_in
(32bit)
– Input
Data Bus
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This
is used to supply the data to the input RAM.
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go
‘Active High’ – Begins Encryption
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This
signal should be made high after the data is completely entered into the
Input RAM . This signal starts the encryption process by reading the data
from the Input RAM and feeding it to the DES. |
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reset
‘Active High’ – Resets all the counters and address pointers to
initial values. |
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This
signal should be made ‘high’ for 100ns and then back ‘low’ before
writing the data into the Input RAM. |
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inst_wr_n
– Write
Enable |
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This
signal is used to write the data present on the data bus (inst_data_in) to
the address location on the address bus (inst_wr_addr) once the data and
the address are available on the respective buses . |
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inst_rd_addr1
(4 bit , expandable to 8bit)
– Output
RAM Read Address |
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This
is used to supply the address to read the stored encrypted data from the
output RAM.
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inst_data_out1(32
bit)
– Output
data bus |
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This
is used to read the encrypted data from the output RAM specified by the
address location present on the address bus (inst_rd_addr1).
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Expanding
the depth of the RAM
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Testing of this block the depth of this RAM was fixed at 16 but is
expandable to 256. Accordingly the bus width will have to be
expanded to 8 bit. |
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this the following changes will have to be done. |
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the design ware RAM block (DW_ram_r_w_a_dff_inst.vhd) change the
‘inst_depth’ to 256 . Accordingly the address bus with at all
places will have to be changed to 8 bits.
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data count is currently set to 2 in the controller.v file . Change
this to (depth/4). |
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From
writing the data into the Input Ram to Obtaining Output
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Encryption block excrypts a 64 bit plain text with a 64 bit
key input . Since the SoC system bus was fixed at 32bit wide we have
split the plain text and the key to two words of 32bits . The first
location of the Input RAM is the LSB of the key and the second
location is the MSB . The third location in the RAM is the LSB of
the plain text and the fourth location is the MSB of the plain text.
This order must be maintained for all the input data. |
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Reset should be made high and then low again |
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Place the address in the address bus of the Input RAM at the rising
edge of the clock |
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Place the data in the data bus of the Input RAM at the next rising
edge |
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Make the inst_wr_n high the next clock for one clock cycle. |
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process must be repeated for each data.
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After the data is written to the RAM the ‘go” signal must be
made high. |
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The
64 bit encrypted data is split into two words of 32 bit width. The
LSB is written in address location ‘0000’ and the MSB is written
in address location ‘0001’. This format continues for all
encrypted data. |
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To read the encrypted data the address must be placed on the
(inst_rd_addr1) Output RAM address bus . |
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