| Problem
1 |
| One
of the important problems that we faced while doing synthesis was feed
throughs in the DES module. |
| "Warning:
In design 'xp_4', there are 48 feed throughs. (LINT-30) Warning: In
design 'xp_4', there are 16 output ports shorted to other output
ports. (LINT-30)" |
| Cause:
A feed through occurs when an input port connects directly to an
output port. |
| Solution:
Design compiler was forced to insert a buffer between input and output
ports using "set_fix_multiple_port_nets -feed throughs". In
order to remove feed throughs in all modules the following tcl script
can be used |
| |
| Problem
2 |
| Appearence
of "assign statement" in the netlist .This created problems
while doing the LVS check as the design compiler would assign some
port to zero if that has to be grounded. resulting in LVS mismatch. |
| Cause:
Assign statements appear due to presence of "tri-state
elements" in the netlist or could be due to Feed throughs |
| Solution:
Design compiler can be issued "verilogout_no_tri = true" to
eliminate assign statements or if assign statements are because of
"feedthroughs" an incremental compiling can be done . |
|
| Problem
3: |
| One
of the design constraints that we faced was maximum fan-outs for
driving pins. |
| Solution:
Issuing the command "set_max_fanout" in design compiler
would set the maximum fan-outs of the driving pins |
|
| Problem
4: |
| We
also faced some clock constraint warnings while doing synthesis. |
| Solution:
If your design has a clock, it is better to give "create_clock
-period clock_pin" to create a clock of certain period giving the
clock pin name |
|
| Problem
5 |
Each
of the modules in the gate-level netlist should be added with VDD and
VSS supply wires.Failing
to add this caused problem while doing Silicon-ensemble |
Solution:
Executed a perl script
which added
supply1 VDD
supply0 VSS
after each module description in the netlist |
|
| Problem
6 |
| VDD
and VSS mismatch in silicon ensemble while importing Netlist
(File--> import --> verilog) |
| Solution:In
the case of tsmc technology,power and ground lines are given as VDD
and VSS Therefore while importing the netlist after importing the lef
, VDD and VSS should be given as input in the "power nets"
and "ground nets" options. |
|
| Problem
7 |
| "Nets
in a loop" error while doing Verify --> Connectivity in
Silicon ensemble |
| Cause:
Suppose that there are 2 ports of the same name and both the ports are
connected to ground.While doing place and route, silicon ensemble
first connects both the ports and then connects one of the ports to
ground. This causes the "net in a loop" error. |
Solution:
A variable option should be changed while doing "wroute".Change
the value of the variable
"wroute.allow.shorts" from true to false |
|
| Problem
8 |
| Warnings
while trying to import the gate-level netlist in ICFB to get Schematic |
Solution:
While we do "File --> import --> verilog" a window
will open where we need to give the netlist name and the Reference
libraries.
Add "basic tsmc18 tsmc18_artisan_test1" in Reference
libraries and
Add "tsmc18_artisan_test1" in Target compile library name |
|
| Problem
9 |
| LVS
mismatch in "terminals" |
| Solution:
Once the DEF is imported to get the layout in ICFB ,add VDD and VSS in
the layout. |
|
| Problem
10: |
| Values
were not written into the RAM properly while doing Post-Synthesis
simulation |
| Solution:
The testbench for
doing Pre-layout simulation and the one used for post-synthesis should
be different. Inorder to write inside the RAM (Post-synthesis) we used
the following statements |