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FFT Standalone Module

Figure 1.0   Interface of FFT Stand Alone Module.


This module was developed Adam Miller at the electrical engineering department at the University of Tennessee.

Inputs/Outputs:
xrsi : Data Input, Real part of complex integer values, 12-bit wide
xisi : Data Input, Imaginary part of complex integer values, 12-bit wide
xrso : Data Output, Real part of complex integer values, 36-bit wide
xiso : Data Output,Imaginary part of complex integer values, 36-bit wide
clk : Control Inputl, Standard Logic
reset_n : Control Input, Standard Logic
load_enable : Control Input, Standard Logic



Figure 1.1   Block Diagram of FFT64.



Description:
The 64-sample pipeline FFT is based on the Radix-22 Single-path delay Feedback architecture.   This architecture processes the input data in the natural order and gives the output in bit-reversed order.   Input data is received one sample per clock cycle and output data is generated one sample per clock cycle.

Data is accepted by the FFT for 64 clock cycles and it starts producing the output at the 64th clock cycle.   The next frame of transform can be computed without pausing due to the pipelined processing of each stage.   The data for each point are synchronized with the rising edge of the clock when the load_enable is active high.   The data is then fed into the FFT core and the output data in bit-reversed order is produced after the 63rd clock cycle.  The next 64-sample data frame can follow the first frame continuously.

Timing and Operation:
Pre-synthesis simulation:
FFT starts accepting the input data after the load_enable goes high.  This input data can be supplied from a textfile or a RAM.  Two 12-bit vectors are sent to the FFT for 64 clock cycles.  After the 63rd clock cycle the FFT starts producing two output vectors, each of 36 bits width, for every clock cycle.





Figure 1.2  Pre-synthesis Simulation of FFT Stand Alone Module (Part 1).  The waveform in this figure shows the input data (xrsi and xisi) being read by the FFT module after the load_enable became high at 200ns.





Figure 1.3  Pre-synthesis Simulation of FFT Stand Alone Module (Part 2).  The output stream (xrso and xiso) starts from the FFT module after the 63rd clock cycle at 6500ns as seen in this figure.   The first three sets of output for the given input stream are:  00FC52D76000000000  00028D78A000000000   007F70280000000000


The output can be written to a textfile or to an output RAM.  In the case of FFT stand alone module, the input is read from a textfile and the output produced is written to another textfile.





Figure 1.4  Pre-synthesis Simulation of FFT Stand Alone Module.  This figure shows the full funcionality of the FFT module.  The inputs to the FFT start at 200ns.





Figure 1.5  Pre-synthesis Simulation of FFT Stand Alone Module.  This figure shows the full funcionality of the FFT module.  The outputs from the FFT start at 6500ns.


Post-layout simulations:

After the presynthesis simulations, the FFT module has been synthesized using Synopsys Design Compiler.   The netlist file, fft.v in this case, is then imported into Silicon Ensemble along with the tsmc18 general constraint file and the tsmc18 6-metal layer layout exchange format file for generating the physical layout.   After the placement and routing, the .dspf and .def files are exported from Silicon Ensemble.  These files are used to generate the .sdf file which is used for the post-layout simulation.





Figure 1.6  Post-layout Simulation of FFT Stand Alone Module (Part 1).   The waveform in this figure shows the input data (xrsi and xisi) being read by the FFT module after the load_enable became high.





Figure 1.7  Post-layout Simulation of FFT Stand Alone Module (Part 2). The waveform in this figure shows the input data (xrsi and xisi) being read by the FFT module after the load_enable became high.  After the 63rd clock cycle, the outputs xrso and xiso start coming out of the FFT.   The first three sets of output data which can be seen in the post-layout simulation are the same as the first three sets of output data in the presynthesis simulation.  The output data from the post-layout simulation can be verified by comparing it's output textfile with the output file of the pre-synthesis simulation. Both those data sets match here implying that the post-layout simulation works.

In the post-layout simulation, the output in each cycle takes some time before reaching a constant value. This can be noticed at the thick green lines before each output cycle.





Figure 1.8  Post-Layout Simulation of FFT Stand Alone Module.  This figure shows the full funcionality of the FFT module and the point where the input starts.  





Figure 1.9  Post-Layout of FFT Stand Alone Module.  This figure shows the full funcionality of the FFT module and the point where the output starts.  

Layouts:
FFT targeted to Xilinx Virtex 1000e:






Figure 1.10  Design FFT on Xilinx Virtex 1000e.   This occupied 22% of the total slices at a frequency of 10 MHz.  






Figure 1.11  Layout generated in Silicon Ensemble  






Figure 1.12  Layout in Virtuoso   The .def file produced in Silicon ensemble is imported into Cadence Virtuoso to generate the above layout.