Source Code:
Testbench:
Conclusions:
The frequency at which the pre-synthesis and the post-layout simulations
were done for both the standalone FFT and the RAM-FFT-RAM modules is 10 MHz.The
post-layout simulations may not produce the expected results for frequency above
that. The output of the standalone FFT module was verified by computing the FFT for
the same input data set in Matlab. The post-layout simulations in case of the FFT and RAM-FFT-RAM were
verified by comparing them with the outputs from the pre-synthesis simulations. Incase of post-layout
simulations the inputs to the modules should be given a few nano seconds after the clock edge
and not exactly at the edge of the clock. The standalone FFT
was targeted to Xilinx Virtex 1000e and the layout was generated. But the RAM-FFT-RAM could not be
targeted to that FPGA. The placement and routing could not proceed after certain point giving a
message that there is not enough space. Performing post-layout simulation is not a difficult task.
But the netlist provided by the synopsys compiler could not be interpreted by Silicon Ensemble correctly
for the FFT. Therefore errors were generated while trying to export the .sdf file from SE, which led to
a wrong post-layout simulation several times. The post-layout simulation worked only after changing
the manner in which the .sdf file was exported. The RAM-FFT-RAM can be extended to be able to communicate
with the AMBA AHB and APB buses.